Encarnación Castillo

According to our database1, Encarnación Castillo authored at least 23 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Cost-Effective Printed Electrodes Based on Emerging Materials Applied to Biosignal Acquisition.
IEEE Access, 2020

Elliptic Curve Cryptography hardware accelerator for high-performance secure servers.
J. Supercomput., 2019

Wearable System for Biosignal Acquisition and Monitoring Based on Reconfigurable Technologies.
Sensors, 2019

An Optimized Measurement Algorithm for Gas Sensors Based on Carbon Nanotubes: Optimizing Sensor Performance and Hardware Resources.
IEEE Internet Things J., 2019

Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.
Sensors, 2018

A new area-efficient BCD-digit multiplier.
Digit. Signal Process., 2017

Classification Algorithms for Fetal QRS Extraction in Abdominal ECG Signals.
Proceedings of the Bioinformatics and Biomedical Engineering, 2017

Comments on "Fast architecture for decimal digit multiplication".
Microprocess. Microsystems, 2016

Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP.
Digit. Signal Process., 2015

Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques.
J. Appl. Math., 2013

Efficient wavelet-based ECG processing for single-lead FHR extraction.
Digit. Signal Process., 2013

One-step wavelet-based processing for wandering and noise removing in ECG signals.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013

Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.
Microprocess. Microsystems, 2012

A reconstruction method for electrical capacitance tomography based on image fusion techniques.
Digit. Signal Process., 2012

Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
Proceedings of the FPL 2008, 2008

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.
Proceedings of the FPL 2007, 2007

Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
Proceedings of the FPL 2007, 2007

IPP Watermarking Technique for IP Core Protection on FPL Devices.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.
Proceedings of the Integrated Circuit and System Design, 2005

Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Intellectual Property Protection for RNS Circuits on FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004