Luís Parrilla Roure

Orcid: 0000-0001-8126-1146

Affiliations:
  • University of Granada, Spain


According to our database1, Luís Parrilla Roure authored at least 40 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces.
Sensors, February, 2024

2023
Toward Sensor Measurement Reliability in Blockchains.
Sensors, December, 2023

Corrections to "Digital implementation of Radial Basis Function Neural Networks Based on Stochastic Computing".
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2023

Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications.
Cryptogr., June, 2023

Digital Implementation of Radial Basis Function Neural Networks Based on Stochastic Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Blockchain-based implementation of Tradable Green Certificates.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

2022
RESEKRA: Remote Enrollment Using SEaled Keys for Remote Attestation.
Sensors, 2022

Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices.
IEEE Internet Things J., 2022

Integration of Hardware Security Modules and Permissioned Blockchain in Industrial IoT Networks.
IEEE Access, 2022

2021
Arithmetic and Algebraic Circuits
Intelligent Systems Reference Library 201, Springer, ISBN: 978-3-030-67265-2, 2021

Window Polarization in PCA-based Analysis of Non-Invasive Fetal ECG recordings.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Simple Single Particle Model for Interpreting Fast Charge Results in Intercalation Batteries.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Elliptic Curve Cryptography hardware accelerator for high-performance secure servers.
J. Supercomput., 2019

Efficient image-based analysis of fruit surfaces using CCD cameras and smartphones.
J. Supercomput., 2019

Wearable System for Biosignal Acquisition and Monitoring Based on Reconfigurable Technologies.
Sensors, 2019

Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.
Sensors, 2018

2017
A new area-efficient BCD-digit multiplier.
Digit. Signal Process., 2017

Classification Algorithms for Fetal QRS Extraction in Abdominal ECG Signals.
Proceedings of the Bioinformatics and Biomedical Engineering, 2017

2016
Comments on "Fast architecture for decimal digit multiplication".
Microprocess. Microsystems, 2016

2015
Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP.
Digit. Signal Process., 2015

2013
Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques.
J. Appl. Math., 2013

Efficient wavelet-based ECG processing for single-lead FHR extraction.
Digit. Signal Process., 2013

One-step wavelet-based processing for wandering and noise removing in ECG signals.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2013

2009
Enhanced gradient-based motion vector coprocessor.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Improved gradient-based motion estimation on reconfigurable platforms.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2007
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
Proceedings of the FPL 2007, 2007

2006
IPP Watermarking Technique for IP Core Protection on FPL Devices.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Intellectual Property Protection for RNS Circuits on FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

2002
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Implementation of the one dimensional discrete cosine transform using the residue number system.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
A new architecture to compute the discrete cosine transform using the quadratic residue number system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
Using PVM for Distributed Logic Minimization in a Network of Computers.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1999

Adaptive Cooperation Between Processors in a Parallel Boltzmann Machine.
Proceedings of the Engineering Applications of Bio-Inspired Artificial Neural Networks, 1999

1998
Testability of AND-EXOR logic vs. AND-OR logic.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Modified Boltzmann Machine for an Efficient Distributed Implementation.
Proceedings of the Biological and Artificial Computation: From Neuroscience to Technology, 1997


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