Uwe Meyer-Bäse

Orcid: 0000-0001-8130-9963

According to our database1, Uwe Meyer-Bäse authored at least 55 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications.
Cryptogr., June, 2023

2022
Hardware-Efficient Decimation with Spectral Shape Approximating the Nth Power of a Dirichlet Kernel.
Circuits Syst. Signal Process., 2022

Graph signal processing to identify biomarkers in brain networks in dementia.
Proceedings of the Medical Imaging 2022: Biomedical Applications in Molecular, 2022

2021
Alternative Data Paths for the Cascaded Integrator-Comb Decimator [Tips & Tricks].
IEEE Signal Process. Mag., 2021

Identifying the diffusion source of dementia spreading in structural brain networks.
Proceedings of the Medical Imaging 2021: Biomedical Applications in Molecular, 2021

Structural Target Controllability of Brain Networks in Dementia.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2019
Pinning observability of competitive neural networks with different time-constants.
Neurocomputing, 2019

2018
Security evaluation of Tree Parity Re-keying Machine implementations utilizing side-channel emissions.
EURASIP J. Inf. Secur., 2018

2017
Dynamical Graph Theory Networks Methods for the Analysis of Sparse Functional Connectivity Networks and for Determining Pinning Observability in Brain Networks.
Frontiers Comput. Neurosci., 2017

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with <i>n</i>-input arithmetic operators.
EURASIP J. Adv. Signal Process., 2017

2016
Code obfuscation using very long identifiers for FFT motion estimation models in embedded processors.
J. Real Time Image Process., 2016

2015
Customized Nios II multi-cycle instructions to accelerate block-matching techniques.
Proceedings of the Real-Time Image and Video Processing 2015, 2015

2014
On the inclusion of prime factors to calculate the theoretical lower bounds in multiplierless single constant multiplications.
EURASIP J. Adv. Signal Process., 2014

Digital Signal Processing with Field Programmable Gate Arrays, 4th Edition
Springer, ISBN: 978-3-642-45308-3, 2014

2013
FIR filter optimization for video processing on FPGAs.
EURASIP J. Adv. Signal Process., 2013

Hardware implementation of machine vision systems: image and video processing.
EURASIP J. Adv. Signal Process., 2013

Multiple constant multiplication with ternary adders.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor.
Sensors, 2012

Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.
Microprocess. Microsystems, 2012

Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture.
Digit. Signal Process., 2012

Selection of Spatiotemporal Features in Breast MRI to Differentiate between Malignant and Benign Small Lesions Using Computer-Aided Diagnosis.
Adv. Artif. Neural Syst., 2012

Multiplatform GPGPU implementation of the active contours without edges algorithm.
Proceedings of the Visual Information Processing XXI, 2012

2011
FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision.
Sensors, 2011

FPGA-Based Acceleration of Block Matching Motion Estimation Techniques.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Robust Bioinspired Architecture for Optical-Flow Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays.
IEEE Trans. Educ., 2010

2009
Enhanced gradient-based motion vector coprocessor.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Improved gradient-based motion estimation on reconfigurable platforms.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Space-efficient simulation of quantum computers.
Proceedings of the 47th Annual Southeast Regional Conference, 2009

2007
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique.
EURASIP J. Adv. Signal Process., 2007

Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
Proceedings of the FPL 2007, 2007

2006
IPP Watermarking Technique for IP Core Protection on FPL Devices.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology.
J. Circuits Syst. Comput., 2005

Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.
J. VLSI Signal Process., 2003

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.
J. VLSI Signal Process., 2003

New power-of-2 RNS scaling scheme for cell-based IC design.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Design and Implementation of RNS-Based Adaptive Filters.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.
J. VLSI Signal Process., 2001

Design of RNS-based distributed arithmetic DWT filterbanks.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
An interspike interval method for computing phase locking from neural firing.
Biol. Cybern., 2000

1999
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Fast implementation of orthogonal wavelet filterbanks using field-programmable logic.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998
A Fast Modified CORDIC - Implementation of Radial Basis Neural Networks.
J. VLSI Signal Process., 1998

Frequency sampling filters with algebraic integers.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Pipelined Hogenauer CIC filters using field-programmable logic and residue number system.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
Artificial implementation of auditory neurons: A comparison of biologically motivated models and a new transfer function oriented model.
Biol. Cybern., 1997

Design of RNS frequency sampling filter banks.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
Convolutional Error Decoding with FPGAs.
Proceedings of the Field-Programmable Logic, 1996

Coherent Demodulation with FPGAs.
Proceedings of the Field-Programmable Logic, 1996

1994
COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA.
Proceedings of the Field-Programmable Logic, 1994


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