Eugene Earlie

According to our database1, Eugene Earlie authored at least 8 papers between 2004 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
Register File Power Reduction Using Bypass Sensitive Compiler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Automatic Design Space Exploration of Register Bypasses in Embedded Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Retargetable pipeline hazard detection for partially bypassed processors.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Bypass aware instruction scheduling for register file power reduction.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.
Proceedings of the 2005 Design, 2005

Aggregating processor free time for energy reduction.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Operation tables for scheduling in the presence of incomplete bypassing.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004


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