Aviral Shrivastava

According to our database1, Aviral Shrivastava authored at least 118 papers between 2000 and 2018.

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Bibliography

2018
A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments.
IEEE Trans. Reliability, 2018

Guest Editorial: Special Issue on Accelerated Computing.
IEEE Trans. Multi-Scale Computing Systems, 2018

EXPERT: Effective and flexible error protection by redundant multithreading.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

URECA: Unified register file for CGRAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

LASER: A hardware/software approach to accelerate complicated loops on CGRAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

RAMP: resource-aware mapping for CGRAs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability.
IEEE Trans. VLSI Syst., 2017

Timestamp Temporal Logic (TTL) for Testing the Timing of Cyber-Physical Systems.
ACM Trans. Embedded Comput. Syst., 2017

Protecting Caches from Soft Errors: A Microarchitect's Perspective.
ACM Trans. Embedded Comput. Syst., 2017

WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory.
ACM Trans. Embedded Comput. Syst., 2017

NEMESIS: A software approach for computing in presence of soft errors.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Reducing code management overhead in software-managed multicores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

InCheck: An In-application Recovery Scheme for Soft Errors.
Proceedings of the 54th Annual Design Automation Conference, 2017

Crossroads: Time-Sensitive Autonomous Intersection Management Technique.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Automatic management of Software Programmable Memories in Many-core Architectures.
IET Computers & Digital Techniques, 2016

Software Coherence Management on Non-coherent Cache Multi-cores.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Margdarshak: A Mobile Data Analytics based Commute Time Estimator cum Route Recommender.
Proceedings of the 3rd International on Workshop on Physical Analytics, 2016

Languages Must Expose Memory Heterogeneity.
Proceedings of the Second International Symposium on Memory Systems, 2016

UrbanEye: An outdoor localization system for public transport.
Proceedings of the 35th Annual IEEE International Conference on Computer Communications, 2016

Splitting functions in code management on scratchpad memories.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Unsupervised annotated city traffic map generation.
Proceedings of the 24th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems, GIS 2016, Burlingame, California, USA, October 31, 2016

nZDC: a compiler technique for near zero silent data corruption.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Time in cyber-physical systems.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

gemV: A validated toolset for the early exploration of system reliability.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Efficient pointer management of stack data for software managed multicores.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
A Software Scheme for Multithreading on CGRAs.
ACM Trans. Embedded Comput. Syst., 2015

Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores.
ACM Trans. Embedded Comput. Syst., 2015

A predictable and command-level priority-based DRAM controller for mixed-criticality systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Enabling multi-threaded applications on hybrid shared memory manycore architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Path selection based acceleration of conditionals in CGRAs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Guidelines to design parity protected write-back L1 data cache.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Optimization of multi-channel BCH error decoding for common cases.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability.
IEEE Trans. Parallel Distrib. Syst., 2014

WCET-aware dynamic code management on scratchpads for Software-Managed Multicores.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Branch-Aware Loop Mapping on CGRAs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Construction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architectures.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Enabling energy efficient reliability in embedded systems through smart cache cleaning.
ACM Trans. Design Autom. Electr. Syst., 2013

Software-based register file vulnerability reduction for embedded processors.
ACM Trans. Embedded Comput. Syst., 2013

Memory performance estimation of CUDA programs.
ACM Trans. Embedded Comput. Syst., 2013

A software-only scheme for managing heap data on limited local memory(LLM) multicore processors.
ACM Trans. Embedded Comput. Syst., 2013

Automatic and efficient heap data management for limited local memory multicore architectures.
Proceedings of the Design, Automation and Test in Europe, 2013

SSDM: smart stack data management for software managed multicores (SMMs).
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs).
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

CMSM: An efficient and effective Code Management for Software Managed Multicores.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Return Data Interleaving for Multi-Channel Embedded CMPs Systems.
IEEE Trans. VLSI Syst., 2012

PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2012

Design of an RNS reverse converter for a new five-moduli special set.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

EPIMap: using epimorphism to map applications on CGRAs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Soft errors: the hardware-software interface.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Memory access optimization in compilation for coarse-grained reconfigurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2011

Static Analysis of Register File Vulnerability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Fast and energy-efficient constant-coefficient FIR filters using residue number system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Enabling Multithreading on CGRAs.
Proceedings of the International Conference on Parallel Processing, 2011

UnSync: A Soft Error Resilient Redundant Multicore Architecture.
Proceedings of the International Conference on Parallel Processing, 2011

CuMAPz: a tool to analyze memory access patterns in CUDA.
Proceedings of the 48th Design Automation Conference, 2011

Branch penalty reduction on IBM cell SPUs via software branch hinting.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Smart cache cleaning: energy efficient vulnerability reduction in embedded processors.
Proceedings of the 14th International Conference on Compilers, 2011

Vector class on limited local memory (LLM) multi-core processors.
Proceedings of the 14th International Conference on Compilers, 2011

Stack data management for Limited Local Memory (LLM) multi-core processors.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors.
IEEE Trans. VLSI Syst., 2010

Partitioning techniques for partially protected caches in resource-constrained embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2010

A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Code Transformations for TLB Power Reduction.
International Journal of Parallel Programming, 2010

B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems.
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

Cache vulnerability equations for protecting data in embedded processor caches from soft errors.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Operation and data mapping for CGRAs with multi-bank memory.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Power-accuracy tradeoffs in human activity transition detection.
Proceedings of the Design, Automation and Test in Europe, 2010

Heap data management for limited local memory (LLM) multi-core processors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Compilation techniques for CGRAs: exploring all parallelization approaches.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Dynamic code mapping for limited local memory systems.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2009

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.
IEEE Trans. VLSI Syst., 2009

A Software-Only Solution to Use Scratch Pads for Stack Data.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Code Transformations for TLB Power Reduction.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A compiler optimization to reduce soft errors in register files.
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

FSAF: File system aware flash translation layer for NAND Flash Memories.
Proceedings of the Design, Automation and Test in Europe, 2009

Static analysis to mitigate soft errors in register files.
Proceedings of the Design, Automation and Test in Europe, 2009

Exploiting residue number system for power-efficient digital signal processing in embedded processors.
Proceedings of the 2009 International Conference on Compilers, 2009

Compiler-managed register file protection for energy-efficient soft error reduction.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A software solution for dynamic stack management on scratch pad memory.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Register File Power Reduction Using Bypass Sensitive Compiler.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Temperature and Process Variations Aware Power Gating of Functional Units.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Power Reduction of Functional Units Considering Temperature and Process Variations.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach.
Proceedings of the 16th International Conference on Multimedia 2008, 2008

Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.
Proceedings of the Distributed Embedded Systems: Design, 2008

SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.
Proceedings of the High Performance Computing, 2008

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.
Proceedings of the Design, Automation and Test in Europe, 2008

Static analysis of processor stall cycle aggregation.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Automatic Design Space Exploration of Register Bypasses in Embedded Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors.
Proceedings of IEEE International Conference on Communications, 2007

Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Smart driver for power reduction in next generation bistable electrophoretic display technology.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Compiler Aided Design of Embedded Computers.
The Compiler Design Handbook, 2nd ed., 2007

2006
Retargetable pipeline hazard detection for partially bypassed processors.
IEEE Trans. VLSI Syst., 2006

Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).
ACM Trans. Design Autom. Electr. Syst., 2006

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006

Bypass aware instruction scheduling for register file power reduction.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Mitigating soft error failures for multimedia applications by selective data protection.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.
Proceedings of the 2005 Design, 2005

Aggregating processor free time for energy reduction.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Compilation techniques for energy reduction in horizontally partitioned cache architectures.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Operation tables for scheduling in the presence of incomplete bypassing.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
Proceedings of the 2002 Design, 2002

2000
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000


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