Nikil D. Dutt

According to our database1, Nikil D. Dutt authored at least 457 papers between 1989 and 2020.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2014, "For contributions to embedded architecture exploration, and service to electronic design automation and embedded systems.".

IEEE Fellow

IEEE Fellow 2008, "For contributions to architecture description languages for the design and exploration of customized processors".

Timeline

Legend:

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PhD thesis 
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Links

Homepages:

On csauthors.net:

Bibliography

2020
Mapping Spiking Neural Networks to Neuromorphic Hardware.
IEEE Trans. VLSI Syst., 2020

2019
HESSLE-FREE: Heterogeneous Systems Leveraging Fuzzy Control for Runtime Resource Management.
ACM Trans. Embedded Comput. Syst., 2019

Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router.
IEEE Trans. Computers, 2019

Hierarchical adaptive Multi-objective resource management for many-core systems.
Journal of Systems Architecture - Embedded Systems Design, 2019

The power impact of hardware and software actuators on self-adaptable many-core systems.
Journal of Systems Architecture - Embedded Systems Design, 2019

Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors.
IACR Cryptology ePrint Archive, 2019

On-Chip Dynamic Resource Management.
Foundations and Trends in Electronic Design Automation, 2019

Post-Quantum Lattice-Based Cryptography Implementations: A Survey.
ACM Comput. Surv., 2019

A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing.
CoRR, 2019

Optimizing Energy Efficiency of Wearable Sensors Using Fog-assisted Control.
CoRR, 2019

The Information Processing Factory: Organization, Terminology, and Definitions.
CoRR, 2019

Personalized Maternal Sleep Quality Assessment: An Objective IoT-based Longitudinal Study.
IEEE Access, 2019

SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Small Memory Footprint Neural Network Accelerators.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Dynamic Computation Migration at the Edge: Is There an Optimal Choice?
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ARGA: Approximate Reuse for GPGPU Acceleration.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

A Real-time PPG Quality Assessment Approach for Healthcare Internet-of-Things.
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019

Energy-efficient and Reliable Wearable Internet-of-Things through Fog-Assisted Dynamic Goal Management.
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019

2018
Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores.
IEEE Trans. Multi-Scale Computing Systems, 2018

ShaVe-ICE: Sharing Distributed Virtualized SPMs in Many-Core Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2018

Synergistic CPU-GPU Frequency Capping for Energy-Efficient Mobile Games.
ACM Trans. Embedded Comput. Syst., 2018

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS.
Proceedings of the IEEE, 2018

Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout.
Neural Networks, 2018

On the feasibility of SISO control-theoretic DVFS for power capping in CMPs.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Domain-specific Accelerators for Ideal Lattice-based Public Key Protocols.
IACR Cryptology ePrint Archive, 2018

HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation.
Embedded Systems Letters, 2018

Guest Editorial: Special Issue on Self-Aware Systems on Chip.
IEEE Design & Test, 2018

MEMCOP: memory-aware co-operative power management governor for mobile games.
Design Autom. for Emb. Sys., 2018

Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

CHIPS-AHOy: a predictable holistic cyber-physical hypervisor for MPSoCs.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Exploring Hybrid Memory Caches in Chip Multiprocessors.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Hierarchical dynamic goal management for IoT systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A Recurrent Neural Network Based Model of Predictive Smooth Pursuit Eye Movement in Primates.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Edge-Assisted Sensor Control in Healthcare IoT.
Proceedings of the IEEE Global Communications Conference, 2018

Trends in On-chip Dynamic Resource Management.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Design methodologies for enabling self-awareness in autonomous systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Gain scheduled control for nonlinear power management in CMPs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Approximation-aware coordinated power/performance management for heterogeneous multi-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018

SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Architecture and Cross-Layer Design Space Exploration.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Microarchitecture-Level SoC Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.
IEEE Trans. VLSI Syst., 2017

Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms.
IEEE Trans. Multi-Scale Computing Systems, 2017

HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT.
ACM Trans. Embedded Comput. Syst., 2017

SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems.
Embedded Systems Letters, 2017

Self-Awareness in Systems on Chip - A Survey.
IEEE Design & Test, 2017

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning.
CoRR, 2017

PoIiCym: rapid prototyping of resource management policies for HMPs.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Dependability evaluation of SISO control-theoretic power managers for processor architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Empowering autonomy through self-awareness in MPSoCs.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

ML-Gov: a machine learning enhanced integrated CPU-GPU DVFS governor for mobile gaming.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Self-awareness in remote health monitoring systems using wearable electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Trends, challenges and needs for lattice-based cryptography implementations: special session.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Exploring fast and slow memories in HMP core types: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Quality-configurable memory hierarchy through approximation: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores.
ACM Trans. Embedded Comput. Syst., 2016

Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective.
ACM Trans. Embedded Comput. Syst., 2016

Automatic management of Software Programmable Memories in Many-core Architectures.
IET Computers & Digital Techniques, 2016

Self-Awareness in Cyber-Physical Systems.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for mobile games.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

HAMEX: heterogeneous architecture and memory exploration framework.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile Gaming.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Approximation knob: power capping meets energy efficiency.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

On Detecting and Using Memory Phases in Multimedia Systems.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

SPARTA: runtime task allocation for energy efficient heterogeneous many-cores.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation.
ACM Trans. Embedded Comput. Syst., 2015

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings.
IEEE Trans. Computers, 2015

DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.
TACO, 2015

A GPU-accelerated cortical neural network model for visually guided robot navigation.
Neural Networks, 2015

Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models.
JETC, 2015

NSF expedition on variability-aware software: Recent results and contributions.
it - Information Technology, 2015

Exploiting Partially-Forgetful Memories for Approximate Computing.
Embedded Systems Letters, 2015

Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors.
Embedded Systems Letters, 2015

Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations.
Proceedings of the 28th International Conference on VLSI Design, 2015

Heat-aware transmission strategies.
Proceedings of the 2015 Information Theory and Applications Workshop, 2015

Thermal sensor allocation for SoCs based on temperature gradients.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Orchestrated application quality and energy storage management in solar-powered embedded systems.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

CARLsim 3: A user-friendly and highly optimized library for the creation of neurobiologically detailed spiking neural networks.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Self-Aware Cyber-Physical Systems-on-Chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Protecting caches against multi-bit errors using embedded erasure coding.
Proceedings of the 20th IEEE European Test Symposium, 2015

Memory-aware cooperative CPU-GPU DVFS governor for mobile games.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Models, abstractions, and architectures: the missing links in cyber-physical systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory.
IEEE Trans. VLSI Syst., 2014

SPMCloud: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud.
ACM Trans. Design Autom. Electr. Syst., 2014

Introduction to Special Issue on Cross-layer Dependable Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2014

Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embedded Comput. Syst., 2014

Embedded RAIDs-on-chip for bus-based chip-multiprocessors.
ACM Trans. Embedded Comput. Syst., 2014

NoC-based fault-tolerant cache design in chip multiprocessors.
ACM Trans. Embedded Comput. Syst., 2014

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Efficient Spiking Neural Network Model of Pattern Motion Selectivity in Visual Cortex.
Neuroinformatics, 2014

FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC).
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Quality-aware mobile graphics workload characterization for energy-efficient DVFS design.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multi-Layer Memory Resiliency.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC).
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

GPGPU accelerated simulation and parameter tuning for neuromorphic applications.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining.
ACM Trans. Embedded Comput. Syst., 2013

Underdesigned and Opportunistic Computing in Presence of Hardware Variability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Categorization and decision-making in a neurobiologically plausible spiking network using a STDP-like learning rule.
Neural Networks, 2013

A large-scale neural network model of the influence of neuromodulatory levels on working memory and behavior.
Front. Comput. Neurosci., 2013

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution.
Design Autom. for Emb. Sys., 2013

A Reliable, Safe, and Secure Run-Time Platform for Cyber Physical Systems.
Proceedings of the 2013 IEEE 6th International Conference on Service-Oriented Computing and Applications, 2013

Vision-inspired global routing for enhanced performance and reliability.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Biologically plausible models of homeostasis and STDP: Stability and learning in spiking neural networks.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.
Proceedings of the International Green Computing Conference, 2013

Outlook for many-core systems: Cloudy with a chance of virtualization.
Proceedings of the 18th IEEE European Test Symposium, 2013

Modeling and analysis of fault-tolerant distributed memories for networks-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2013

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

ARGO: Aging-aware GPGPU register file allocation.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Design space exploration and parameter tuning for neuromorphic applications.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

VISA synthesis: Variation-aware Instruction Set Architecture synthesis.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Variability-aware memory management for nanoscale computing.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
EAVE: Error-Aware Video Encoding Supporting Extended Energy/QoS Trade-offs for Mobile Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2012

xTune: A formal methodology for cross-layer tuning of mobile embedded systems.
ACM Trans. Embedded Comput. Syst., 2012

Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embedded Comput. Syst., 2012

Combining code reordering and cache configuration.
ACM Trans. Embedded Comput. Syst., 2012

Introduction to special section SCPS'09.
ACM Trans. Embedded Comput. Syst., 2012

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Resilient dependable cyber-physical systems: a middleware perspective.
J. Internet Services and Applications, 2012

Guest Editorial Special Section on Memory Architectures and Organization.
Embedded Systems Letters, 2012

HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design.
Embedded Systems Letters, 2012

Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing.
Proceedings of the 25th International Conference on VLSI Design, 2012

Software Controlled Memories for Scalable Many-Core Architectures.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Keynote speach.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC).
Proceedings of the 11th Workshop on Adaptive and Reflective Middleware, 2012

PTL: PCM Translation Layer.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Spiking neuron model of basal forebrain enhancement of visual attention.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

An advanced course design for mobile embedded software through Android programming.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012

AVid: Annotation driven video decoding for hybrid memories.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

VaMV: Variability-aware Memory Virtualization.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

ViPZonE: OS-level memory variability-driven physical address zoning for energy savings.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A novel NoC-based design for fault-tolerance of last-level caches in CMPs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
A Multi-Granularity Power Modeling Methodology for Embedded Processors.
IEEE Trans. VLSI Syst., 2011

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

An Efficient Simulation Environment for Modeling Large-Scale Cortical Processing.
Front. Neuroinform., 2011

Neuromorphic modeling abstractions and simulation of large-scale cortical networks.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

TrustGeM: Dynamic trusted environment generation for chip-multiprocessors.
Proceedings of the HOST 2011, 2011

E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories.
Proceedings of the Design, Automation and Test in Europe, 2011

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays.
Proceedings of the Design, Automation and Test in Europe, 2011

SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.
Proceedings of the 14th International Conference on Compilers, 2011

A Formal Methodology for Compositional Cross-Layer Optimization.
Proceedings of the Formal Modeling: Actors, Open Systems, Biological Systems, 2011

2010
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.
IEEE Trans. VLSI Syst., 2010

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.
IEEE Trans. VLSI Syst., 2010

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.
TRETS, 2010

Partitioning techniques for partially protected caches in resource-constrained embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2010

Towards reverse engineering the brain: Modeling abstractions and simulation frameworks.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity.
Proceedings of the HOST 2010, 2010

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010

E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010

PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.
IEEE Trans. VLSI Syst., 2009

Fast Configurable-Cache Tuning With a Unified Second-Level Cache.
IEEE Trans. VLSI Syst., 2009

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.
IEEE Trans. VLSI Syst., 2009

System-level PVT variation-aware power exploration of on-chip communication architectures.
ACM Trans. Design Autom. Electr. Syst., 2009

Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.
IEEE Trans. Industrial Informatics, 2009

Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embedded Comput. Syst., 2009

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors.
Neural Networks, 2009

Brain Derived Vision Algorithm on High Performance Architectures.
International Journal of Parallel Programming, 2009

CODES+ISSS 2007 guest editors' introduction.
Design Autom. for Emb. Sys., 2009

Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata.
Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009

A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Live Demonstration: Computing Spike-based Convolutions on GPUs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Computing Spike-based Convolutions on GPUs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors.
Proceedings of the International Joint Conference on Neural Networks, 2009

Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

TRAM: A tool for Temperature and Reliability Aware Memory Design.
Proceedings of the Design, Automation and Test in Europe, 2009

Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Specification-driven directed test generation for validation of pipelined processors.
ACM Trans. Design Autom. Electr. Syst., 2008

Fast exploration of bus-based communication architectures at the CCATB abstraction.
ACM Trans. Embedded Comput. Syst., 2008

Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.
ACM Trans. Embedded Comput. Syst., 2008

Register File Power Reduction Using Bypass Sensitive Compiler.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Real-time analysis of resource-constrained distributed systems by simulation-guided model checking.
SIGBED Review, 2008

Trends in Emerging On-Chip Interconnect Technologies.
IPSJ Trans. System LSI Design Methodology, 2008

Using FORAY Models to Enable MPSoC Memory Optimizations.
International Journal of Parallel Programming, 2008

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
IJES, 2008

Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach.
Proceedings of the 16th International Conference on Multimedia 2008, 2008

Compiler driven data layout optimization for regular/irregular array access patterns.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.
Proceedings of the Distributed Embedded Systems: Design, 2008

Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems.
Proceedings of the Distributed Embedded Systems: Design, 2008

Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

A framework for memory-aware multimedia application mapping on chip-multiprocessors.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Constraint Refinement for Online Verifiable Cross-Layer System Adaptation.
Proceedings of the Design, Automation and Test in Europe, 2008

Memory-aware NoC Exploration and Design.
Proceedings of the Design, Automation and Test in Europe, 2008

ESL hand-off: fact or EDA fiction?
Proceedings of the 45th Design Automation Conference, 2008

Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Quo vadis, BTSoC (Billion Transistor SoC)?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst., 2007

DRDU: A data reuse analysis technique for efficient scratch-pad memory management.
ACM Trans. Design Autom. Electr. Syst., 2007

Automatic Design Space Exploration of Register Bypasses in Embedded Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices.
IEEE Journal on Selected Areas in Communications, 2007

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.
Design Autom. for Emb. Sys., 2007

Quality-Based Backlight Optimization for Video Playback on Handheld Devices.
Adv. in MM, 2007

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements.
Proceedings of the Parallel Computing: Architectures, 2007

Annotation Integration and Trade-off Analysis for Multimedia Applications.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Data Reuse Driven Memory and Network-On-Chip Co-Synthesis.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Modeling of Software-Hardware Complexes.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

System level power estimation methodology with H.264 decoder prediction IP case study.
Proceedings of the 25th International Conference on Computer Design, 2007

Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2007

A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems.
Proceedings of the Formal Methods for Open Object-Based Distributed Systems, 2007

Performance estimation of distributed real-time embedded systems by discrete event simulations.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
Proceedings of the 44th Design Automation Conference, 2007

Software controlled memory layout reorganization for irregular array access patterns.
Proceedings of the 2007 International Conference on Compilers, 2007

LEAF: A System Level Leakage-Aware Floorplanner for SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Compiler Aided Design of Embedded Computers.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

2006
Retargetable pipeline hazard detection for partially bypassed processors.
IEEE Trans. VLSI Syst., 2006

FABSYN: floorplan-aware bus architecture synthesis.
IEEE Trans. VLSI Syst., 2006

Energy efficient watermarking on mobile devices using proxy-based partitioning.
IEEE Trans. VLSI Syst., 2006

ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. VLSI Syst., 2006

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.
IEEE Trans. VLSI Syst., 2006

Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).
ACM Trans. Design Autom. Electr. Syst., 2006

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006

A retargetable framework for instruction-set architecture simulation.
ACM Trans. Embedded Comput. Syst., 2006

Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh.
Mobile Computing and Communications Review, 2006

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Bypass aware instruction scheduling for register file power reduction.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Video Stream Annotations for Energy Trade-offs in Multimedia Applications.
Proceedings of the 5th International Symposium on Parallel and Distributed Computing (ISPDC 2006), 2006

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Annotation Based Multimedia Streaming Over Wireless Networks.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Formal performance evaluation of AMBA-based system-on-chip designs.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Software annotations for power optimization on mobile devices.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automatic identification of application-specific functional units with architecturally visible storage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
Proceedings of the 43rd Design Automation Conference, 2006

System-level power-performance trade-offs in bus matrix communication architecture synthesis.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Floorplan driven leakage power aware IP-based SoC design space exploration.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Mitigating soft error failures for multimedia applications by selective data protection.
Proceedings of the 2006 International Conference on Compilers, 2006

Constraint-driven bus matrix synthesis for MPSoC.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Editorial.
ACM Trans. Design Autom. Electr. Syst., 2005

Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.
IEEE Trans. Computers, 2005

A methodology for validation of microprocessors using symbolic simulation.
IJES, 2005

An Introduction to the Plasma Language.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices.
Proceedings of the Networking, 2005

An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

Probability Based Power Aware Error Resilient Coding.
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A first look at the interplay of code reordering and configurable caches.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.
Proceedings of the 2005 Design, 2005

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.
Proceedings of the 2005 Design, 2005

Functional Coverage Driven Test Generation for Validation of Pipelined Processors.
Proceedings of the 2005 Design, 2005

FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations.
Proceedings of the 2005 Design, 2005

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
Proceedings of the 2005 Design, 2005

Floorplan-aware automated synthesis of bus-based communication architectures.
Proceedings of the 42nd Design Automation Conference, 2005

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.
Proceedings of the 42nd Design Automation Conference, 2005

Aggregating processor free time for energy reduction.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Compilation techniques for energy reduction in horizontally partitioned cache architectures.
Proceedings of the 2005 International Conference on Compilers, 2005

Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005

A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Automated throughput-driven synthesis of bus-based communication architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Functional verification of programmable embedded architectures - a top-down approach.
Springer, ISBN: 978-0-387-26143-0, 2005

2004
Coordinated parallelizing compiler optimizations and high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 2004

Processor-memory coexploration using an architecture description language.
ACM Trans. Embedded Comput. Syst., 2004

Modeling and validation of pipeline specifications.
ACM Trans. Embedded Comput. Syst., 2004

IDAP: a tool for high-level power estimation of custom array structures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Using global code motions to improve the quality of results for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts.
IEICE Transactions, 2004

Dynamic Backlight Adaptation for Low-Power Handheld Devices.
IEEE Design & Test of Computers, 2004

A Top-Down Methodology for Microprocessor Validation.
IEEE Design & Test of Computers, 2004

Synthesis-driven Exploration of Pipelined Embedded Processors.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Functional Verification of Pipelined Processors: A Case Study.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

FIFO power optimization for on-chip networks.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 2004

Functional Validation of Programmable Architectures.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Graph-Based Functional Test Program Generation for Pipelined Processors.
Proceedings of the 2004 Design, 2004

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies.
Proceedings of the 2004 Design, 2004

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.
Proceedings of the 2004 Design, 2004

Automatic Tuning of Two-Level Caches to Embedded Applications.
Proceedings of the 2004 Design, 2004

Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2004 Design, 2004

Energy-Aware System Design for Wireless Multimedia.
Proceedings of the 2004 Design, 2004

Extending the transaction level modeling approach for fast communication architecture exploration.
Proceedings of the 41th Design Automation Conference, 2004

Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices.
Proceedings of the 41th Design Automation Conference, 2004

Introduction of local memory elements in instruction set extensions.
Proceedings of the 41th Design Automation Conference, 2004

Operation tables for scheduling in the presence of incomplete bypassing.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Fast exploration of bus-based on-chip communication architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Analytical models for leakage power estimation of memory array structures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Efficient search space exploration for HW-SW partitioning.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Energy-Aware Adaptations for End-to-End Videostreaming to Mobile Handheld Devices.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

Tuning Caches to Applications for Low-Energy Embedded Systems.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Adaptive low-power address encoding techniques using self-organizing lists.
IEEE Trans. VLSI Syst., 2003

RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions.
IEEE Trans. VLSI Syst., 2003

Access pattern-based memory and connectivity architecture exploration.
ACM Trans. Embedded Comput. Syst., 2003

Compilation Approach for Coarse-Grained Reconfigurable Architectures.
IEEE Design & Test of Computers, 2003

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications.
Design Autom. for Emb. Sys., 2003

Configurable Processors for Embedded Computing.
IEEE Computer, 2003

A Methodology for Accurate Modeling of Energy Dissipation in Array Structures.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

A Methodology for Validation of Microprocessors using Equivalence Checking.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Integrated power management for video streaming to mobile handheld devices.
Proceedings of the Eleventh ACM International Conference on Multimedia, 2003

An algorithm for mapping loops onto coarse-grained reconfigurable architectures.
Proceedings of the 2003 Conference on Languages, 2003

Energy-efficient instruction set synthesis for application-specific processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

FORGE: A Framework for Optimization of Distributed Embedded Systems Software.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Reducing Compilation Time Overhead in Compiled Simulators.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Interface Synthesis using Memory Mapping for an FPGA Platform.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Data Organization Exploration for Low-Energy Address Buses.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

On-chip Stack Based Memory Organization for Low Power Embedded Architectures.
Proceedings of the 2003 Design, 2003

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs.
Proceedings of the 2003 Design, 2003

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
Proceedings of the 40th Design Automation Conference, 2003

An efficient retargetable framework for instruction-set simulation.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Driving agenda for systems research.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.
Proceedings of the International Conference on Compilers, 2003

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Memory architecture exploration for programmable embedded systems.
Kluwer, ISBN: 978-1-4020-7324-3, 2003

2002
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Efficient Power Reduction Techniques for Time Multiplexed Address Buses.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Automatic functional test program generation for pipelined processors using model checking.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Memory Architectures for Embedded Systems-On-Chip.
Proceedings of the High Performance Computing, 2002

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.
Proceedings of the 2002 Design, 2002

An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
Proceedings of the 2002 Design, 2002

Memory System Connectivity Exploration.
Proceedings of the 2002 Design, 2002

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints.
Proceedings of the 2002 Design, 2002

Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

V-SAT: A visual specification and analysis tool for system-on-chip exploration.
Journal of Systems Architecture, 2001

Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Design & Test of Computers, 2001

Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors.
IEEE Design & Test of Computers, 2001

Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Functional abstraction driven design space exploration of heterogeneous programmable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Conditional speculation and its effects on performance and area for high-level snthesis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

APEX: Access Pattern Based Memory Architecture Exploration.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Low power address encoding using self-organizing lists.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Automatic validation of pipeline specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Access pattern based local memory customization for low power embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Speculation Techniques for High Level Synthesis of Control Intensive Designs.
Proceedings of the 38th Design Automation Conference, 2001

New directions in compiler technology for embedded systems (embedded tutorial).
Proceedings of ASP-DAC 2001, 2001

2000
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98).
IEEE Trans. VLSI Syst., 2000

On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.
ACM Trans. Design Autom. Electr. Syst., 2000

High-level library mapping for memories.
ACM Trans. Design Autom. Electr. Syst., 2000

Aggressive Memory-Aware Compilation.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

Customizing Software Toolkits for Embedded Systems-On-Chip.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

MIST: An Algorithm for Memory Miss Traffic Management.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Verification of in-order execution in pipelined processors.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Architecture Exploration of Parameterizable EPIC SOC Architectures.
Proceedings of the 2000 Design, 2000

How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Proceedings of the 2000 Design, 2000

Memory aware compilation through accurate timing extraction.
Proceedings of the 37th Conference on Design Automation, 2000

Program path analysis to bound cache-related preemption delay in preemptive real-time systems.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Low-power memory mapping through reducing address bus activity.
IEEE Trans. VLSI Syst., 1999

Local memory exploration and optimization in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers, 1999

On the rapid prototyping and design of a wireless communication system on a chip (abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Design of a set-top box system on a chip (abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability.
Proceedings of the 1999 Design, 1999

1998
Incorporating DRAM access modes into high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Copy Elimination for Parallelizing Compilers.
Proceedings of the Languages and Compilers for Parallel Computing, 1998

Embedded memories in system design - from technology to systems architecture.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Data Cache Sizing for Embedded Processor Applications.
Proceedings of the 1998 Design, 1998

Memory size estimation for multimedia applications.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
Memory data organization for improved cache performance in embedded processor applications.
ACM Trans. Design Autom. Electr. Syst., 1997

A unified lower bound estimation technique for high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Behavioral Array Mapping into Multiport Memories Targeting Low Power.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Architectural Exploration and Optimization of Local Memory in Embedded Systems.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Improving cache Performance Through Tiling and Data Alignment.
Proceedings of the Solving Irregularly Structured Problems in Parallel, 1997

A Data Alignment Technique for Improving Cache Performance.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Exploiting off-chip memory access modes in high-level synthesis.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Efficient utilization of scratch-pad memory in embedded processor applications.
Proceedings of the European Design and Test Conference, 1997

Library mapping for memories.
Proceedings of the European Design and Test Conference, 1997

1996
High-level library mapping for arithmetic components.
IEEE Trans. VLSI Syst., 1996

Optimal register assignment to loops for embedded code generation.
ACM Trans. Design Autom. Electr. Syst., 1996

Elimination of redundant memory traffic in high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Memory Organization for Improved Data Cache Performance in Embedded Processors.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Low-power mapping of behavioral arrays to multiple memories.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

A Method for Register Allocation to Loops in Multiple Register File Architectures.
Proceedings of IPPS '96, 1996

Reducing Address Bus Transitions for Low Power Memory Mapping.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A hypergraph-based model for port allocation on multiple-register-file VLIW architectures.
International Journal of Parallel Programming, 1995

1995 high level synthesis design repository.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

A comprehensive estimation technique for high-level synthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Incorporating compiler feedback into the design of ASIPs.
Proceedings of the 1995 European Design and Test Conference, 1995

Design reuse through high-level library mapping.
Proceedings of the 1995 European Design and Test Conference, 1995

Reclocking for high-level synthesis.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Ultra Fine-Grain Template-Driven Synthesis.
Proceedings of the Seventh International Conference on VLSI Design, 1994

An Empirical Study on the Effects of Physical Design in High-Level Synthesis.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Rapid Technology Projection for High-Level Synthesis.
Proceedings of the Seventh International Conference on VLSI Design, 1994

An algorithm for the allocation of functional units from realistic RT component libraries.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

Partitioning of Variables for Multiple-Register-File VLIW Architectures.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Comprehensive lower bound estimation from behavioral descriptions.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Integrating program transformations in the memory-based synthesis of image and video algorithms.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Unified code generation approach using mutation scheduling.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Minimization of Memory Traffic in High-Level Synthesis.
Proceedings of the 31st Conference on Design Automation, 1994

Design Reuse: Fact or Fiction? (Panel).
Proceedings of the 31st Conference on Design Automation, 1994

1993
Rapid estimation for parameterized components in high-level synthesis.
IEEE Trans. VLSI Syst., 1993

A language for designer controlled behavioral synthesis.
Integration, 1993

Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Regular schedules for scalable design of IIR filters.
Proceedings of the European Design Automation Conference 1993, 1993

High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Representation for the Binding of RT-Component Functionality to HDL Behavior.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Benchmarking and the Art of Syntesis Tool Comparison.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Equivalent design representations and transformations for interactive scheduling.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Harmonic scheduling of linear recurrences for digital filter design.
Proceedings of the conference on European design automation, 1992

Youn-Long Steve Lin
Springer, ISBN: 978-1-4615-3636-9, 1992

1991
Bridging High-Level Synthesis to RTL Technology Libraries.
Proceedings of the 28th Design Automation Conference, 1991

1990
Design Synthesis and Silicon Compilation.
IEEE Design & Test of Computers, 1990

LEGEND: A Language for Generic Component Library Description.
Proceedings of the 1990 Internation Conference on Computer Languages, 1990

An Intermediate Representation for Behavioral Synthesis.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Designer Controlled Behavioral Synthesis.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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