Eugene Shragowitz

According to our database1, Eugene Shragowitz authored at least 29 papers between 1985 and 2016.

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Bibliography

2016
Adaptive Partitions.
Encyclopedia of Algorithms, 2016

2008
Adaptive Partitions.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

2006
Iterative-Constructive Standard Cell Placer for High Speed and Low Power.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2003
Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like Models.
J. Comb. Optim., 2003

Transaction-based waveform analysis for IP selection.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Net criticality revisited: an effective method to improve timing in physical design.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
Wire segmenting for buffer insertion based on RSTP-MSP.
Theor. Comput. Sci., 2001

Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic Design.
International Journal on Artificial Intelligence Tools, 2001

1998
Application of fuzzy logic in computer-aided VLSI design.
IEEE Trans. Fuzzy Systems, 1998

1995
Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

Generic fuzzy logic CAD development tool.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Fuzzy logic approach to VLSI placement.
IEEE Trans. VLSI Syst., 1994

1993
An adaptive timing-driven placement for high performance VLSIs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Bounds on net lengths for high-speed PCB.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Prelayout timing analysis of cell-based VLSI designs.
Comput. Aided Des., 1992

Fuzzy Logic Approach to Placement Problem.
Proceedings of the 29th Design Automation Conference, 1992

1991
An analytical approach to floorplan design and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Bounds on Net Delays for Physical Design of Fast Circuits.
Proceedings of the VLSI 91, 1991

Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement.
Proceedings of the 28th Design Automation Conference, 1991

1990
Timing Constraints for Correct Performance.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

An Adaptive Timing-Driven Layout for High Speed VLSI.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Critical path issue in VLSI design.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
A Hypercube Algorithm for the 0/1 Knapsack Problem.
J. Parallel Distributed Comput., 1988

1987
A global router based on a multicommodity flow model.
Integr., 1987

A Hypecube Algorithm for the 0/1 Knapsack Problem.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Simulated annealing and combinatorial optimization.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Automated layout synthesis in the YASC silicon compiler.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Experiments with simulated annealing.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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