Gerald E. Sobelman

According to our database1, Gerald E. Sobelman authored at least 94 papers between 1984 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Adaptive Directional Lifting Wavelet Transform VLSI Architecture.
Signal Processing Systems, 2019

Memory Segment Matching Network Based Image Geo-Localization.
IEEE Access, 2019

2018
Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
Hardware Efficient Massive MIMO Detector Based on the Monte Carlo Tree Search Method.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Stochastic computing implementation of trigonometric and hyperbolic functions.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Network-on-Chip for Turbo Decoders.
IEEE Trans. VLSI Syst., 2016

Cascaded Network Body Channel Model for Intrabody Communication.
IEEE J. Biomedical and Health Informatics, 2016

An Intra-Iterative Interference Cancellation Detector for Large-Scale MIMO Communications Based on Convex Optimization.
IEEE Trans. on Circuits and Systems, 2016

Sparse Code Multiple Access Decoding Based on a Monte Carlo Markov Chain Method.
IEEE Signal Process. Lett., 2016

Improved design of digital 1-D and 2-D notch filters using general feedback structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems.
IEEE Trans. VLSI Syst., 2015

Stochastic Iterative MIMO Detection System: Algorithm and Hardware Design.
IEEE Trans. on Circuits and Systems, 2015

A low complexity algorithm and architecture for MIMO detection without QR decomposition.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Network-coding-based distributed relay scheme for PLC networks.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Stochastic MIMO Detector Based on the Markov Chain Monte Carlo Algorithm.
IEEE Trans. Signal Processing, 2014

A database-driven Ant Colony Algorithm for PLC networking.
IEICE Electronic Express, 2014

High performance MIMO detector based on bidirectional path preserving trellis search.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Iterative Computation of FIR MIMO MMSE-DFE With Flexible Complexity-Performance Tradeoff.
IEEE Trans. Signal Processing, 2013

Scaling, Offset, and Balancing Techniques in FFT-Based BP Nonbinary LDPC Decoders.
IEEE Trans. on Circuits and Systems, 2013

Low complexity state metric compression technique in turbo decoder.
IEICE Electronic Express, 2013

FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A gradient-controlled proportionate technique for acoustic echo cancellation.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

A gradient-controlled improved proportionate multi-delay filter.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Generic Mixed-Radix FFT Pruning.
IEEE Signal Process. Lett., 2012

A novel hardware-oriented decoding algorithm for non-binary LDPC codes.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes.
IEEE Trans. VLSI Syst., 2011

Reconfigurable baseband processing architecture for communication.
IET Computers & Digital Techniques, 2011

A high-throughput LDPC decoder architecture for high-rate WPAN systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

General lattice wave digital filter with phase compensation scheme.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FFT implementation with Multi-operand floating point units.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Wideband spectrum sensing using the all-phase FFT.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Bus Energy Consumption for Multilevel Signals.
IEEE Trans. on Circuits and Systems, 2010

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform.
IEICE Transactions, 2010

Frequency domain adaptive tap partial update adaptive algorithm for network echo cancellation.
Proceedings of the IEEE International Conference on Acoustics, 2010

Novel and flexible Complex Coefficient Linear phase IIR filters for communications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Memory size reduction for LDPC layered decoders.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Sparse LMS with segment zero attractors for adaptive estimation of sparse signals.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Technical program co-chairs' message.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Gradient-based target localization in robotic sensor networks.
Pervasive and Mobile Computing, 2009

Mesh-star Hybrid NoC Architecture with CDMA Switch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Optimality of Bus-Invert Coding.
IEEE Trans. on Circuits and Systems, 2008

Adaptive quantization in min-sum based irregular LDPC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Cscan: A Correlation-based Scheduling Algorithm for Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2008

An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture.
Proceedings of the International Conference on Embedded Software and Systems, 2008

A heterogeneous reconfigurable baseband architecture for wireless LAN transceivers.
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

Reconfigurable baseband processing platform for communication systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Flexible LDPC decoder architecture for high-throughput applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
High Speed Look-Ahead LMS Detector for MIMO Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Implementation of a Multi-band Pulsed-OFDM Transceiver.
VLSI Signal Processing, 2006

TwinsNet: A Cooperative MIMO Mobile Sensor Network.
Proceedings of the Ubiquitous Intelligence and Computing, Third International Conference, 2006

Gradient-Driven Target Acquisition in Mobile Wireless Sensor Networks.
Proceedings of the Mobile Ad-hoc and Sensor Networks, Second International Conference, 2006

Network-on-chip link analysis under power and performance constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

NIUGAP: low latency network interface architecture with Gray code for networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Network-on-chip quality-of-service through multiprotocol label switching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Modeling and verification of high-speed wired links with Verilog-AMS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Noise Model Analysis of Optimized Mixed-Radix Structures for Pulsed OFDM.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Hardware channel model for ultra wideband systems.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Low-Power Bus Transform Coding for Multilevel Signals.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

FPGA-Based Design of a Pulsed-OFDM System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Parallel FFT computation with a CDMA-based network-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

FPGA-Based CDMA Switch for Networks-on-Chip.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
VLSI Design Of Digit-Serial FPGA Architecture.
Journal of Circuits, Systems, and Computers, 2004

Simultaneous bidirectional PAM-4 link with built-in self-test.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Design techniques for Pulsed Static CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simultaneous bidirectional signaling with adaptive pre-emphasis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance of N-tone sigma-delta modulators for UWB-OFDM.
Proceedings of IEEE International Conference on Communications, 2004

2003
Performance evaluation and optimal design for FPGA-based digit-serial DSP functions.
Computers & Electrical Engineering, 2003

2002
Efficient digit-serial FIR filters with skew-tolerant domino.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A robust self-resetting CMOS 32-bit parallel adder.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

High-speed add-compare-select units using locally self-resetting CMOS.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Digit-serial modular multiplication using skew-tolerant domino CMOS.
Proceedings of the IEEE International Conference on Acoustics, 2001

High-speed CORDIC implementations using advanced circuit techniques.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Time borrowing in high-speed functional units using skew-tolerant domino circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

ATM switch design using code division multiple access techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Elliptic Curve Scalar Multiplier Design Using FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems, 1999

1998
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Digit-Serial DSP Library for Optimized FPGA Configuration.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
A New Low-Voltage Full Adder Circuit.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995
Low-Power Multiplier Design Using Delayed Evaluation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
A programmable floating-point cell for systolic signal processing.
VLSI Signal Processing, 1993

1991
Design and Implementation of a Low-Cost Systolic Array System.
Journal of Circuits, Systems, and Computers, 1991

Simulation-based design of programmable systolic arrays.
Computer-Aided Design, 1991

A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation.
Proceedings of the 28th Design Automation Conference, 1991

1990
Design and programming of a flexible, cost-effective systolic array cell for digital signal processing.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1990

Fast Switch-Level Fault Simulation Using Functional Fault Modeling.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1986
Automated layout synthesis in the YASC silicon compiler.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Yet another silicon compiler.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1984


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