Faeze Noruzpur

According to our database, Faeze Noruzpur authored at least 4 papers between 2017 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology.

Faeze Noruzpur, Sina Mahdavi, Maryam Poreh, Shima Tayyeb Ghasemi

Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2017

A novel APS pixel level rearrangement to increase the fill factor and SNR in 0.35μm CMOS technology.

Ali Baradaran Rezaeii, Faeze Noruzpur, Sina Mahdavi

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

A new fast rail-to-rail continuous-time common-mode feedback circuit.

Sina Mahdavi, Faeze Noruzpur, Esmaii Ghadimi, Tohid Moradi Khanshan

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

An extendable global clock high-speed binary counter compatible to the FPGA CLBs.

Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017