Sarang Kazeminia

According to our database, Sarang Kazeminia authored at least 21 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A low-jitter leakage-free digitally calibrated phase locked loop.

Sarang Kazeminia, Arefeh Soltani

Comput. Electr. Eng., 2020

2019

A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs.

Sarang Kazeminia

Integr., 2019

2018

A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs.

Sarang Kazeminia, Khayrollah Hadidi

Integr., 2018

2017

An extendable global clock high-speed binary counter compatible to the FPGA CLBs.

Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

2016

Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs.

Sarang Kazeminia, Sina Mahdavi, Khayrollah Hadidi

Proceedings of the 2016 MIXDES, 2016

Bulk controlled offset cancellation mechanism for single-stage latched comparator.

Sarang Kazeminia, Sina Mahdavi, Reza Gholamnejad

Proceedings of the 2016 MIXDES, 2016

A 800MS/s, 150µV input-referred offset single-stage latched comparator.

Sarang Kazeminia, Sina Mahdavi

Proceedings of the 2016 MIXDES, 2016

Programmable incrementing/decrementing binary accumulator for high-speed calibration loops.

Arefeh Soltani, Roozbeh Abdollahi, Sarang Kazeminia

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs.

Sarang Kazeminia, Arefeh Soltani

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch.

Sarang Kazeminia, Arefeh Soltani

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump.

Sarang Kazeminia, Sobhan Sofimowloodi, Khayrollah Hadidi

J. Circuits Syst. Comput., 2015

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs.

Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei

J. Circuits Syst. Comput., 2015

A digitally assisted 20MHz-600MHz 16-phase DLL enhanced with dynamic gain control loop.

Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi

Proceedings of the European Conference on Circuit Theory and Design, 2015

2013

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs.

Sarang Kazeminia, Obalit Shino, Ehsan Haghighi, Khayrollah Hadidi

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2011

A 500 MS/s 600 µW 300 µm² Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process.

Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei

IEICE Trans. Electron., 2011

Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage.

Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, Mohammad-Naghi Azarmanesh

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection.

Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption.

Mohammad Soleimani, Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing.

Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

High Speed High Precision voltage-Mode Max and Min Circuits.

Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi

J. Circuits Syst. Comput., 2007

An Open Loop Phase Shifter and Frequency Synthesizer.

Sarang Kazeminia, Khayrollah Hadidi

Proceedings of the 14th IEEE International Conference on Electronics, 2007