Farshad Khunjush

According to our database1, Farshad Khunjush authored at least 19 papers between 2006 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 



On csauthors.net:


Accurate compressive data gathering in wireless sensor networks using weighted spatio-temporal compressive sensing.
Telecommunication Systems, 2018

Distributed semi-adaptive compressive sensing data collection in wireless sensor networks.
Int. J. Communication Systems, 2018

Optimal data aggregation tree in wireless sensor networks based on improved river formation dynamics.
Computational Intelligence, 2018

Adaptive sparse matrix representation for efficient matrix-vector multiplication.
The Journal of Supercomputing, 2016

A statistical performance analyzer framework for OpenCL kernels on Nvidia GPUs.
The Journal of Supercomputing, 2015

SEATS: smart energy-aware task scheduling in real-time cloud computing.
The Journal of Supercomputing, 2015

A two-tier design space exploration algorithm to construct GPU performance model.
Journal of Systems Architecture - Embedded Systems Design, 2015

A Cooperative Two-Tier Energy-Aware Scheduling for Real-Time Tasks in Computing Clouds.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

A Two-Tier Design Space Exploration Algorithm to Construct a GPU Performance Predictor.
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

Migration-less Energy-Aware Task Scheduling Policies in Cloud Environments.
Proceedings of the 28th International Conference on Advanced Information Networking and Applications Workshops, 2014

A parallel memetic algorithm on GPU to solve the task scheduling problem in heterogeneous environments.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

A Novel Implementation of Double Precision and Real Valued ICA Algorithm for Bioinformatics Applications on GPUs.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Using indirection to minimize message delivery latency on cache-less many-core architectures.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

Single-port and multi-port collective communication operations on single and dual Cell BE processor systems.
IJCNDS, 2011

Hiding message delivery latency using Direct-to-Cache-Transfer techniques in message passing environments.
Microprocess. Microsystems, 2009

Extended characterization of DMA transfers on the Cell BE processor.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Comparing Direct-to-Cache Transfer Policies to TCP/IP and M-VIA During Receive Operations in MPI Environments.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment.
SIGARCH Computer Architecture News, 2006

Lazy direct-to-cache transfer during receive operations in a message passing environment.
Proceedings of the Third Conference on Computing Frontiers, 2006