Masoud Daneshtalab

According to our database1, Masoud Daneshtalab authored at least 163 papers between 2006 and 2020.

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Bibliography

2020
ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights.
IEEE Micro, 2020

2019
An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip.
The Journal of Supercomputing, 2019

Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router.
IEEE Access, 2019

A Cloud Based Super-Optimization Method to Parallelize the Sequential Code's Nested Loops.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

SoFA: A Spark-oriented Fog Architecture.
Proceedings of the IECON 2019, 2019

NeuroPower: Designing Energy Efficient Convolutional Neural Network Architecture for Embedded Systems.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019

A Qualitative Comparison Model for Application Layer IoT Protocols.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019

Multi-objective Optimization of Real-Time Task Scheduling Problem for Distributed Environments.
Proceedings of the 6th Conference on the Engineering of Computer Based Systems, 2019

TOT-Net: An Endeavor Toward Optimizing Ternary Neural Networks.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Design Challenges in Hardware Development of Time-Sensitive Networking: A Research Plan.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

2018
A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks.
IEEE Micro, 2018

Parallel imperialist competitive algorithms.
Concurrency and Computation: Practice and Experience, 2018

Chapter Three - Multiobjectivism in Dark Silicon Age.
Advances in Computers, 2018

Integrating Learning, Optimization, and Prediction for Efficient Navigation of Swarms of Drones.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Reconfigurable Network-on-Chip for 3D Neural Network Accelerators.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

Designing Compact Convolutional Neural Network for Embedded Stereo Vision Systems.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

ADONN: Adaptive Design of Optimized Deep Neural Networks for Embedded Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Using Optimization, Learning, and Drone Reflexes to Maximize Safety of Swarms of Drones.
Proceedings of the 2018 IEEE Congress on Evolutionary Computation, 2018

A Customized Processing-in-Memory Architecture for Biological Sequence Alignment.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Customizing Clos Network-on-Chip for Neural Networks.
IEEE Trans. Computers, 2017

CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era.
Microprocess. Microsystems, 2017

Optimizing scheduling for heterogeneous computing systems using combinatorial meta-heuristic solution.
Proceedings of the 2017 IEEE SmartWorld, 2017

Safety-Aware Control of Swarms of Drones.
Proceedings of the Computer Safety, Reliability, and Security, 2017

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Hierarchal Placement of Smart Mobile Access Points in Wireless Sensor Networks Using Fog Computing.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Optimal smart mobile access point placement for maximal coverage and minimal communication.
Proceedings of the Fifth European Conference on the Engineering of Computer-Based Systems, 2017

Parallel Forwarding for Efficient Bandwidth Utilization in Networks-on-Chip.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems.
IEEE Trans. Computers, 2016

TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs.
IEEE Trans. Computers, 2016

Non-Blocking Testing for Network-on-Chip.
IEEE Trans. Computers, 2016

A pareto-optimal runtime power budgeting scheme for many-core systems.
Microprocess. Microsystems, 2016

Many-core System-on-Chip: architectures and applications.
Microprocess. Microsystems, 2016

Special issue on energy efficient methods and systems in the emerging cloud era.
J. Comput. Syst. Sci., 2016

Introduction to the Special Section on On-chip parallel and network-based systems.
Comput. Electr. Eng., 2016

Hierarchical approach for hybrid wireless Network-on-chip in many-core era.
Comput. Electr. Eng., 2016

Placement of Smart Mobile Access Points in Wireless Sensor Networks and Cyber-Physical Systems Using Fog Computing.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Efficient Congestion-Aware Scheme for Wireless on-Chip Networks.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

PICA: Multi-population Implementation of Parallel Imperialist Competitive Algorithms.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

Multi-population parallel imperialist competitive algorithm for solving systems of nonlinear equations.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Fault-tolerant 3-D network-on-chip design using dynamic link sharing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
In-order delivery approach for 2D and 3D NoCs.
The Journal of Supercomputing, 2015

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs.
Microprocess. Microsystems, 2015

Special Issue on Emerging Many-Core Systems for Exascale Computing.
JETC, 2015

An efficient runtime power allocation scheme for many-core systems inspired from auction theory.
Integr., 2015

On-chip parallel and network-based systems.
Integr., 2015

WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems.
Embedded Systems Letters, 2015

A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers.
Computing, 2015

Special issue on on-chip parallel and network-based systems.
Computing, 2015

Introduction to the special issue on NoC-based many-core architectures.
Comput. Electr. Eng., 2015

Reconfigurable communication fabric for efficient implementation of neural networks.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Parallel Implementation of Fuzzified Pattern Matching Algorithm on GPU.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Dynamic Application Mapping Algorithm for Wireless Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

FIST: A Framework to Interleave Spiking Neural Networks on CGRAs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Automated Power and Latency Management in Heterogeneous 3D NoCs.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

CuPAN - High Throughput On-chip Interconnection for Neural Networks.
Proceedings of the Neural Information Processing - 22nd International Conference, 2015

Fine-grained runtime power budgeting for networks-on-chip.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Adaptive load balancing in learning-based approaches for many-core embedded systems.
The Journal of Supercomputing, 2014

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
ACM Trans. Embedded Comput. Syst., 2014

Editorial: Special issue on design challenges for many-core processors.
ACM Trans. Embedded Comput. Syst., 2014

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing.
IEEE Trans. Computers, 2014

Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs.
Microprocess. Microsystems, 2014

Special issue on many-core embedded systems.
Microprocess. Microsystems, 2014

High Performance Pattern Matching on Heterogeneous Platform.
J. Integrative Bioinformatics, 2014

Introduction to the Special Issue on Network-on-Chip Architectures.
Comput. Electr. Eng., 2014

A novel non-minimal turn model for highly adaptive routing in 2D NoCs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Integration of AES on Heterogeneous Many-Core System.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Heterogeneous Parallelization of Aho-Corasick Algorithm.
Proceedings of the 8th International Conference on Practical Applications of Computational Biology & Bioinformatics, 2014

Silicon synapse designs for VLSI neuromorphic platform.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Improved Route Selection Approaches using Q-learning framework for 2D NoCs.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

HiWA: A hierarchical Wireless Network-on-Chip architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

NeuroCGRA: A CGRA with support for neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Exploring NoC jitter effect on simulation of spiking neural networks.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Highly adaptive and congestion-aware routing for 3D NoCs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

TransPar: Transformation based dynamic Parallelism for low power CGRAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Parameterized AES-Based Crypto Processor for FPGAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Fault tolerant and highly adaptive routing for 2D NoCs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Rescuing healthy cores against disabled routers.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Adaptive power allocation for many-core systems inspired from multiagent auction model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Special issue on network-based many-core embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2013

A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.
Journal of Systems Architecture - Embedded Systems Design, 2013

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.
J. Comput. Syst. Sci., 2013

Towards a Configurable Many-core Accelerator for FPGA-based embedded systems.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

An exploration of heterogeneous systems.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Efficient application mapping in resource limited homogeneous NoC-based manycore systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

FPGA implementation of AES-based crypto processor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy.
Proceedings of the Design, Automation and Test in Europe, 2013

CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Smart hill climbing for agile dynamic mapping in many-core systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

MD: Minimal path-based fault-tolerant routing in on-Chip Networks.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Memory-Efficient On-Chip Network With Adaptive Interfaces.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Adaptive Input-Output Selection Based On-Chip Router Architecture.
J. Low Power Electronics, 2012

Adaptive reinforcement learning method for networks-on-chip.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Transport layer aware design of network interface in many-core systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Optimized Q-learning model for distributing traffic in on-Chip Networks.
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

Dual Congestion Awareness scheme in On-Chip Networks.
Proceedings of the 3rd IEEE International Conference on Networked Embedded Systems for Every Application, 2012

CoNA: Dynamic application mapping for congestion reduction in many-core systems.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

NoC-AXI interface for FPGA-based MPSoC platforms.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A generic adaptive path-based routing method for MPSoCs.
Journal of Systems Architecture - Embedded Systems Design, 2011

Agent-based on-chip network using efficient selection method.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Exploration of MPSoC monitoring and management systems.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Efficient congestion-aware selection method for on-chip networks.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

High-performance on-chip network platform for memory-on-processor architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Using Routing Agents for Improving the Quality of Service in General Purpose Networks.
Proceedings of the PECCS 2011, 2011

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.
Proceedings of the NOCS 2011, 2011

CorreComm: A formal hierarchical framework for communication designs.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Q-learning based congestion-aware routing algorithm for on-chip network.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Refinement-Based Modeling of 3D NoCs.
Proceedings of the Fundamentals of Software Engineering - 4th IPM International Conference, 2011

Formal Modeling of Multicast Communication in 3D NoCs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Cluster-based topologies for 3D stacked architectures.
Proceedings of the 8th Conference on Computing Frontiers, 2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

HIBS - Novel inter-layer bus structure for stacked architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
EDXY - A low cost congestion-aware routing algorithm for network-on-chips.
Journal of Systems Architecture - Embedded Systems Design, 2010

HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

A Low-Latency and Memory-Efficient On-chip Network.
Proceedings of the NOCS 2010, 2010

Performance Analysis of 3D NoCs Partitioning Methods.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

High-Performance TSV Architecture for 3-D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Input-Output Selection Based Router for Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Power-aware NoC router using central forecasting-based dynamic virtual channel allocation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Partitioning methods for unicast/multicast traffic in 3D NoC architecture.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

CMIT - A novel cluster-based topology for 3D stacked architectures.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips.
J. Low Power Electronics, 2009

Low-distance path-based multicast routing algorithm for network-on-chips.
IET Computers & Digital Techniques, 2009

Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
PAMPR: Power-aware and minimum path routing algorithm for NoCs.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
HW/SW architecture for soft-error cancellation in real-time operating system.
IEICE Electronic Express, 2007

Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion based design error diagnosis for core-based SoCs.
Proceedings of the 2007 IEEE International SOC Conference, 2007

On-Chip Verification of NoCs Using Assertion Processors.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

System Level Voltage Scheduling Technique Using UML-RT Model.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Ant colony based routing architecture for minimizing hot spots in NOCs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006


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