Florian Fricke

Orcid: 0000-0002-6622-3202

According to our database1, Florian Fricke authored at least 14 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2022
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy Using a Novel Data Augmentation Method.
IEEE Trans. Emerg. Top. Comput., 2022

Edge GPU based on an FPGA Overlay Architecture using PYNQ.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

2021
A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
An Integrated on-Silicon Verification Method for FPGA Overlays.
J. Electron. Test., 2019

Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
CGRA Tool Flow for Fast Run-Time Reconfiguration.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications.
CoRR, 2017

Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
A Rapid Prototyping Method to Reduce the Design Time in Commercial High-Level Synthesis Tools.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Redesign of an educational robot platform using web-based programming.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

A Design Methodology for the Next Generation Real-Time Vision Processors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016


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