Michael Hübner

Orcid: 0000-0002-1790-3869

Affiliations:
  • BTU Cottbus-Senftenberg, Institute for Informatics, Germany
  • Ruhr University Bochum, ESIT, Germany
  • University of Karlsruhe, ITIV, Germany


According to our database1, Michael Hübner authored at least 271 papers between 2003 and 2024.

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Bibliography

2024
DeepTest: Using Machine Learning for Generating new Testsequences.
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

Embedded Multi-Core Code Generation with Cross-Layer Parallelization.
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024

2023
A New Chaos-Based PRNG Hardware Architecture Using the HUB Fixed-Point Format.
IEEE Trans. Instrum. Meas., 2023

A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy Using a Novel Data Augmentation Method.
IEEE Trans. Emerg. Top. Comput., 2022

Reduced Precision DWC: An Efficient Hardening Strategy for Mixed-Precision Architectures.
IEEE Trans. Computers, 2022

Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion.
Sensors, 2022

InjectMeAI - Software Module of an Autonomous Injection Humanoid.
Sensors, 2022

STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Edge GPU based on an FPGA Overlay Architecture using PYNQ.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

A distributed Embedded Systems IoT platform and Associated services Supporting Shopping Cart for Disabled People.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

Health Monitoring of Milling Tools under Distinct Operating Conditions by a Deep Convolutional Neural Network model.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
A Manycore Vision Processor for Real-Time Smart Cameras.
Sensors, 2021

Aging-Aware Parallel Execution.
IEEE Embed. Syst. Lett., 2021

Performance analysis of application-specific instruction-set routers in networks-on-chip.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021

DeepTest: How Machine Learning Can Improve the Test of Embedded Systems.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

Deep Learning in Signal Linearization for Harmonic Imaging Application.
Proceedings of the 18th IEEE International Symposium on Biomedical Imaging, 2021

Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Einsatz von Deep Learning für den Test Eingebetteter Systeme.
Proceedings of the 51. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2021 - Computer Science & Sustainability, Berlin, Germany, 27. September, 2021

The SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservices.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

AITIA: Embedded AI Techniques for Industrial Applications.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Towards Machine Learning Support for Embedded System Tests.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Guest Editorial Note: Special Issue on Applied Reconfigurable Computing.
J. Signal Process. Syst., 2020

A Machine Learning Methodology for Cache Memory Design Based on Dynamic Instructions.
ACM Trans. Embed. Comput. Syst., 2020

Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications.
J. Electron. Test., 2020

Guest Editors' Introduction: SBCCI 2018.
IEEE Des. Test, 2020

VLSI for Next Generation CE.
IEEE Consumer Electron. Mag., 2020

Toward an ICT-Based Service Oriented Health Care Paradigm.
IEEE Consumer Electron. Mag., 2020

Flexible hardware architectures for robust Cyberphysical systems.
Proceedings of the Signal Processing: Algorithms, 2020

A Survey on Machine Learning Approaches to ECG Processing.
Proceedings of the Signal Processing: Algorithms, 2020

TIRUB: A Safety and Energy-Aware Scheduling Algorithm.
Proceedings of the Signal Processing: Algorithms, 2020

A Management Technique for Concurrent Access to a Reconfigurable Accelerator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications.
Proceedings of the IEEE Latin-American Test Symposium, 2020

(Special Topic Submission) Enabling Domain-Specific Architectures with an Open-Source Soft-Core GPGPU.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Reduced-Precision DWC for Mixed-Precision GPUs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Deep Learning Utilization in Beamforming Enhancement for Medical Ultrasound.
Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

AITIA: Embedded AI Techniques for Embedded Industrial Applications.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology.
J. Parallel Distributed Comput., 2019

An Integrated on-Silicon Verification Method for FPGA Overlays.
J. Electron. Test., 2019

Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

IP Core Identification in FPGA Configuration Files using Machine Learning Techniques.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
General-Purpose Computing with Soft GPUs on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018

Guest Editorial Circuit and System Design Automation for Internet of Things.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Special issue: Design and architectures for real-time signal and image processing.
J. Real Time Image Process., 2018

A Scalable Approach for Hardware Semiformal Verification.
CoRR, 2018

Towards a Safety and Energy Aware protocol for Wireless Communication.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

An Application Specific Framework for HLS-based FPGA Design of Articulated Robot Inverse Kinematics.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hardware/Software Codesign for Convolutional Neural Networks Exploiting Dynamic Partial Reconfiguration on PYNQ.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Design and Open Source Implementation of a Reconfigurable Hardware Model Predicitive Controller Using Online Optimization.
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

Design of an efficient Communication Architecture for Cyber-Physical Production Systems.
Proceedings of the 14th IEEE International Conference on Automation Science and Engineering, 2018

Runtime Adaptive Cache for the LEON3 Processor.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Dynamic Partial Reconfigurable Overlay Framework for Python.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

CGRA Tool Flow for Fast Run-Time Reconfiguration.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
System-level design space identification for Many-Core Vision Processors.
Microprocess. Microsystems, 2017

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications.
CoRR, 2017

Tackling The New Health-Care Paradigm Through Service Robotics: Unobtrusive, efficient, reliable, and modular solutions for assisted-living environments.
IEEE Consumer Electron. Mag., 2017

Towards a type 0 hypervisor for dynamic reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Floating-Point Arithmetic Using GPGPU on FPGAs.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Semiformal Verification of Software-Controlled Connections.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Access Network Generation for Efficient Debugging of FPGAs.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Hardware Accelerator Framework Approach for Dynamic Partial Reconfigurable Overlays on Xilinx PYNQ.
Proceedings of the 47. Jahrestagung der Gesellschaft für Informatik, 2017

A dynamic partial reconfigurable overlay concept for PYNQ.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

An open reconfigurable research platform as stepping stone to exascale high-performance computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A rapid control prototyping platform methodology for decentralized automation.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

A Machine Learning Methodology for Cache Recommendation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

Towards adaptive and efficient bottling plants in a cyber physical production system environment.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Information Fusion of Conflicting Input Data.
Sensors, 2016

A resampling method for parallel particle filter architectures.
Microprocess. Microsystems, 2016

Introduction to the special section on FPGAs Technology and Applications.
Comput. Electr. Eng., 2016

Enabling indoor object localization through Bluetooth beacons on the RADIO robot platform.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Multi-level parallelism analysis and system-level simulation for many-core Vision processor design.
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016

Enabling Dynamic Reconfiguration of Numerical Methods for the Robotic Motion Control Task.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A Rapid Prototyping Method to Reduce the Design Time in Commercial High-Level Synthesis Tools.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A dynamic cache reconfiguration platform for soft real-time systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Integer computations with soft GPGPU on FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FGPU: An SIMT-Architecture for FPGAs.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Development of advanced driver assistance systems using LabVIEW and a car simulator.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

Redesign of an educational robot platform using web-based programming.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Computation and communication challenges to deploy robots in assisted living environments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A Design Methodology for the Next Generation Real-Time Vision Processors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

Efficient Camera Input System and Memory Partition for a Vision Soft-Processor.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Precise Navigation of Small Agricultural Robots in Sensitive Areas with a Smart Plant Camera.
J. Imaging, 2015

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

ViPES 2015 - Preface.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

FPGA based traffic sign detection for automotive camera systems.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Configurable cache tuning with a victim cache.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Scalable modular hardware platform for FPGA based industrial radar flowmeters.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Message from chairs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Adaptive computing in real-time applications.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

A Framework to the Design and Programming of Many-Core Focal-Plane Vision Processors.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

The value of FPGAs as reconfigurable hardware enabling Cyber-Physical Systems.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

A Fully Parallel Particle Filter Architecture for FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A Framework for Supporting Adaptive Fault-Tolerant Solutions.
ACM Trans. Embed. Comput. Syst., 2014

Special issue on design and architectures of real-time image processing in embedded systems.
J. Real Time Image Process., 2014

OFDM/WDM PON With Laserless, Colorless 1 Gb/s ONUs Based on Si-PIC and Slow IC.
JOCN, 2014

An application scenario for dynamically reconfigurable FPGAs.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Design of an attention detection system on the Zynq-7000 SoC.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

An adaptive victim cache scheme.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A high-level analysis of a multi-core vision processor using SystemC and TLM2.0.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Future Trends on Adaptive Processing Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Development of driver assistance systems using virtual hardware-in-the-loop.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Multi-FPGA reconfigurable system for accelerating MATLAB simulations.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Instruction Set Optimization for Application Specific Processors.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
JITPR: A framework for supporting fast application's implementation onto FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2013

MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems.
ACM Trans. Embed. Comput. Syst., 2013

Introduction to the special section on multiprocessor system-on-chip for cyber-physical systems.
ACM Trans. Embed. Comput. Syst., 2013

Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Dynamic and partial reconfiguration of Zynq 7000 under Linux.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Bi-directional ultra-dense polarization-diverse OFDM/WDM PON with laserless colorless 1Gb/s ONUs based on Si PICs and <417 MHz mixed-signal ICs.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

ViPES Introduction.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Introduction to the Special Issue on ReCoSoC 2011.
ACM Trans. Reconfigurable Technol. Syst., 2012

Single-Laser 325 Tbit/s Nyquist WDM Transmission.
JOCN, 2012

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration.
Int. J. Reconfigurable Comput., 2012

Single-laser 32.5 Tbit/s Nyquist WDM transmission
CoRR, 2012

A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Adaptive processor architecture - invited paper.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012


A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Invited paper: On-chip monitoring for adaptive heterogeneous multicore systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Determination of on-chip temperature gradients on reconfigurable hardware.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

On Dynamic Run-time Processor Pipeline Reconfiguration.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

RAW Introduction.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Time and frequency synchronization for ultra-high speed OFDM systems.
Proceedings of the International Conference on Computing, Networking and Communications, 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Virtualization of heterogeneous and adaptive multi-core/multi-board systems.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Hardware / Software Virtualization for the Reconfigurable Multicore Platform.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Invasive manycore architectures.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Analysis of error detection schemes: Toolchain support and hardware/software implications.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

Realtime PCI Express monitoring for self adaptive reconfigurable systems.
Proceedings of the International Multi-Conference on Systems, Signals & Devices, 2012

FPGA system-on-chip solution for a field oriented hybrid stepper motor control.
Proceedings of the International Multi-Conference on Systems, Signals & Devices, 2012

2011
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010).
Int. J. Reconfigurable Comput., 2011

Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems.
Int. J. Reconfigurable Comput., 2011

Operating System for Runtime Reconfigurable Multiprocessor Systems.
Int. J. Reconfigurable Comput., 2011

Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT.
Int. J. Reconfigurable Comput., 2011

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform.
Int. J. Parallel Program., 2011

Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Approach of an FPGA based adaptive stepper motor control system.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Dynamic Processor Reconfiguration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Adaptive Multi-client Network-on-Chip Memory.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Power and performance optimization through MPI supported dynamic voltage and frequency scaling.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.
Proceedings of the Design, Automation and Test in Europe, 2011

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Run-time resource instantiation for fault tolerance in FPGAs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems.
ACM Trans. Reconfigurable Technol. Syst., 2010

Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Reliability Analysis and Improvement in Nano Scale Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems.
Proceedings of the 19th International Conference on Computer Communications and Networks, 2010

Reconfigurable Hardware for Power-over-Fiber Applications.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

High Performance Architectures and Compilers.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks.
Proceedings of the Fifth International Conference on Bio-Inspired Computing: Theories and Applications, 2010

Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems.
Microprocess. Microsystems, 2009

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.
J. Real Time Image Process., 2009

Selected Papers from ReCoSoC 2008.
Int. J. Reconfigurable Comput., 2009

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip.
Int. J. Reconfigurable Comput., 2009

Method for improving performance in online routing of reconfigurable nano architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

BRICK: a multi-context expression grained reconfigurable architecture.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A multi-core signal processor for heterogeneous reconfigurable computing.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Dynamic reconfigurable mixed-signal architecture for safety critical applications.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Current Trends on Reconfigurable Computing.
Int. J. Reconfigurable Comput., 2008

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC.
IEEE Des. Test Comput., 2008

Towards Novel Approaches in Design Automation for FPGA Power Optimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A framework for dynamic 2D placement on FPGAs.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Runtime adaptive multi-processor system-on-chip: RAMPSoC.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
Proceedings of the FPL 2008, 2008

New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
Proceedings of the FPL 2008, 2008

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
Proceedings of the FPL 2008, 2008

Data path driven waveform-like reconfiguration.
Proceedings of the FPL 2008, 2008


Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2008

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Proceedings of the Design, Automation and Test in Europe, 2008

Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Data reallocation by exploiting FPGA configuration mechanisms.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Dynamic and Partial FPGA Exploitation.
Proc. IEEE, 2007

New tool support and architectures in adaptive reconfigurable computing.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Communication Architectures for Dynamically Reconfigurable FPGA Designs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
Proceedings of the FPL 2007, 2007

Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
Proceedings of the FPL 2007, 2007

A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures.
Proceedings of the FPL 2007, 2007

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
Proceedings of the FPL 2007, 2007

2006
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Run-time reconfigurabilility and other future trends.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Physical 2D Morphware and Power Reduction Methods for Everyone.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
On-demand FPGA run-time system for flexible and dynamical reconfiguration.
Int. J. Embed. Syst., 2005

Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation.
Int. J. Embed. Syst., 2005

I Models and Tools for the Dynamic Reconfiguration of FPGAs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

An FPGA Run-Time System for Dynamical On-Demand Reconfiguration.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
Proceedings of the Field Programmable Logic and Application, 2004

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
Proceedings of the Field Programmable Logic and Application, 2004

Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003


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