Jones Yudi Mori

Orcid: 0000-0001-6707-853X

Affiliations:
  • Ruhr University Bochum, Germany (2018)


According to our database1, Jones Yudi Mori authored at least 23 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2024
Improved Design for Hardware Implementation of Graph-Based Large Margin Classifiers for Embedded Edge Computing.
IEEE Trans. Neural Networks Learn. Syst., January, 2024

2023
Design of an Advanced System-on-Chip Architecture for Chaotic Image Encryption.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A Locomotion Algorithm for an Apodal Robot to Climb and Descend Steps.
Proceedings of the Synergetic Cooperation Between Robots and Humans - Proceedings of the CLAWAR 2023 Conference, 2023

2022
Evaluating a Machine Learning-based Approach for Cache Configuration.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021
A Manycore Vision Processor for Real-Time Smart Cameras.
Sensors, 2021

2020
A Machine Learning Methodology for Cache Memory Design Based on Dynamic Instructions.
ACM Trans. Embed. Comput. Syst., 2020

A manycore vision processor architecture for embedded applications.
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

An IoT solution for load monitoring and tracking of garbage-truck fleets.
Proceedings of the IEEE Conference on Industrial Cyberphysical Systems, 2020

2018
Development of design framework for parallel data processing hardware architectures.
PhD thesis, 2018

General-Purpose Computing with Soft GPUs on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2018

2017
System-level design space identification for Many-Core Vision Processors.
Microprocess. Microsystems, 2017

A Machine Learning Methodology for Cache Recommendation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Multi-level parallelism analysis and system-level simulation for many-core Vision processor design.
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016

A Rapid Prototyping Method to Reduce the Design Time in Commercial High-Level Synthesis Tools.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A Design Methodology for the Next Generation Real-Time Vision Processors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

Efficient Camera Input System and Memory Partition for a Vision Soft-Processor.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
A Framework to the Design and Programming of Many-Core Focal-Plane Vision Processors.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

2014
A high-level analysis of a multi-core vision processor using SystemC and TLM2.0.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Future Trends on Adaptive Processing Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

2013
Development of a stereo vision measurement architecture for an underwater robot.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots.
Int. J. Reconfigurable Comput., 2012

Kernel analysis for architecture design trade off in convolution-based image filtering.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011
FPGA-based image processing for omnidirectional vision on mobile robots.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011


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