Francisco J. Rodriguez-Navarrete

According to our database, Francisco J. Rodriguez-Navarrete authored at least 5 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging.

Francisco J. Rodriguez-Navarrete, German Alonso Pinedo Diaz, L. A. Luna-Rodriguez, Susana Ortega-Cisneros, Luis Pizano-Escalante, Juan José Raygoza-Panduro

IEEE Access, 2025

2024

Vector Accelerator Unit for Caravel.

Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, Luis Pizano-Escalante, Juan José Raygoza-Panduro

IEEE Embed. Syst. Lett., March, 2024

Macro Memory Cell Generator for SKY130 PDK.

Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, German Alonso Pinedo Diaz, Miguel Rivera-Acosta, Francisco J. Rodriguez-Navarrete, Uriel Jaramillo-Toral, Cristian Torres González, Juan Carlos Garcia Lopez

IEEE Access, 2024

RISC- Vcito: A Multicycle Tiny Processor Implemented with SKY130 PDK.

Martin Gonzalez-Perez, Susana Ortega-Cisneros, Francisco J. Rodriguez-Navarrete, German Alonso Pinedo Diaz, Emilio Isaac Baungarten-Leon, Miguel Rivera-Acosta

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2022

Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface.

L. A. Luna-Rodriguez, Francisco J. Rodriguez-Navarrete, Susana Ortega-Cisneros, Miguel Rivera-Acosta, Jorge Rivera Dominguez, Juan José Raygoza-Panduro

Proceedings of the 19th International Conference on Electrical Engineering, 2022