Susana Ortega-Cisneros

Orcid: 0000-0001-6646-1529

According to our database1, Susana Ortega-Cisneros authored at least 54 papers between 1996 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture in Sky130 CMOS Enabling High-Density Modular Integration.
IEEE Access, 2026

2025
Seeding Algorithm for Bipolar Stochastic Computing for Polynomial Approximations.
IEEE Embed. Syst. Lett., December, 2025

On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix.
IEEE Embed. Syst. Lett., February, 2025

Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques.
IEEE Embed. Syst. Lett., February, 2025

Integrated Circuit Design - Tape-out Process with Open-Source Tools
Springer Briefs in Computer Science, Springer, ISBN: 978-3-031-92107-0, 2025

Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging.
IEEE Access, 2025

Implementation of a 16:1 Multiplexer and 1:16 Demultiplexer on a Single Chip Using Sky130 PDK and Open-Source EDA Tools for Silicluster.
Proceedings of the 33rd IFIP/IEEE International Conference on Very Large Scale Integration, 2025

When AI Turns Malicious: Unethical Use of LLMs for Hardware Design.
Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025

Reconfigurable hardware architecture for arbitrary-size banded sparse matrix-by-vector multiplication.
Proceedings of the IEEE Latin-American Conference on Communications, 2025

Analog Blocks for 8-Bit SAR ADC: Rail-to-Rail Comparator and Two-Stage Operational Amplifier Designed with Open-Source Tools and Sky130 PDK.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays.
IEEE Embed. Syst. Lett., March, 2024

Vector Accelerator Unit for Caravel.
IEEE Embed. Syst. Lett., March, 2024

Real-Time Database Systems - Fundamentals, Architectures and Applications
Springer Briefs in Computer Science, Springer, ISBN: 978-3-031-44229-2, 2024

Exception Handling - Fundamentals and Programming
Springer Briefs in Computer Science, Springer, ISBN: 978-3-031-50680-2, 2024

Macro Memory Cell Generator for SKY130 PDK.
IEEE Access, 2024

Automated IC Design Flow Using Open-Source Tools and 180 nm PDK.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

RISC- Vcito: A Multicycle Tiny Processor Implemented with SKY130 PDK.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Transition from Synchronous to Asynchronous Systems with Minimal Logic Changes.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

On the Novel Design and FPGA Implementation of a Fuzzy PD Control for a DC Motor.
Proceedings of the 21st International Conference on Electrical Engineering, 2024

2022
A Novel Framework for Fast Feature Selection Based on Multi-Stage Correlation Measures.
Mach. Learn. Knowl. Extr., 2022

Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface.
Proceedings of the 19th International Conference on Electrical Engineering, 2022

2021
Resolution Enhancement of Spatial Parametric Methods via Regularization.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021

Parameter Selection Criteria for Tomo-SAR Focusing.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021

3D Simulation-Based Acoustic Wave Resonator Analysis and Validation Using Novel Finite Element Method Software.
Sensors, 2021

Statistical Regularization as an Alternative to Model Order Selection.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021

2020
Automatic Cropping of Retinal Fundus Photographs using Convolutional Neural Networks.
Res. Comput. Sci., 2020

Artificial Intelligence-Based Referral System for Patients With Diabetic Retinopathy.
Computer, 2020

2019
Design and Evaluation of a USB Isolator for Medical Instrumentation.
IEEE Trans. Instrum. Meas., 2019

Digital Implementation via FPGA of Controllers for Active Control of Ground Vehicles.
IEEE Trans. Ind. Informatics, 2019

2018
Pedestrian Detection and Tracking Using a Dynamic Vision Sensor.
Computación y Sistemas, 2018

2017
Conformal Geometric Algebra Voting Scheme Implemented in Reconfigurable Devices for Geometric Entities Extraction.
IEEE Trans. Ind. Electron., 2017

American Sign Language Alphabet Recognition Using a Neuromorphic Sensor and an Artificial Neural Network.
Sensors, 2017

2015
HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision.
Computación y Sistemas, 2015

Editorial.
Computación y Sistemas, 2015

FPGA-based startup for AC electric drives: Application to a greenhouse ventilation system.
Comput. Ind., 2015

An image processor for convolution and correlation of binary images implemented in FPGA.
Proceedings of the 12th International Conference on Electrical Engineering, 2015

Design and implementation of a DC motor control using Field Programmable Analog Arrays.
Proceedings of the 12th International Conference on Electrical Engineering, 2015

A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Discrete-time modeling and control of a boost converter by means of a variational integrator and sliding modes.
J. Frankl. Inst., 2014

Implementation of a NARX neural network in a FPGA for modeling the inverse characteristics of power amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Characterization technique to implement self-timed cells for VLSI design blocks.
Proceedings of the 11th International Conference on Electrical Engineering, 2014

Space-time AER protocol receiver asynchronously controlled on FPGA.
Proceedings of the 11th International Conference on Electrical Engineering, 2014

FPGA Implementation of a NARX Network for Modeling Nonlinear Systems.
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2014

Real Time Hardware Accelerator for Image Filtering.
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2014

2012
Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control.
IEEE Trans. Ind. Electron., 2012

Discontinuous output regulation for a DC-to-AC boost converter.
Proceedings of the 9th International Conference on Electrical Engineering, 2012

2011
Discrete-time sensorless control of permanent magnet synchronous motors.
Proceedings of the 8th International Conference on Electrical Engineering, 2011

2008
Hardware Implementation of an Optimal Pole Placement Controller for a Liquid Level System.
Res. Comput. Sci., 2008

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System.
Int. J. Reconfigurable Comput., 2008

2007
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs.
J. Univers. Comput. Sci., 2007

2005
FPGA implementation of a synchronous and self-timed neuroprocessor.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Rapid prototyping of a self-timed ALU with FPGAs.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

1996
Electronic implementation for competitive neural network: a prototype.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996


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