Fulvio Spagna

According to our database, Fulvio Spagna authored at least 8 papers between 2000 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol.

Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2018

Clock and data recovery systems.

Fulvio Spagna

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2010

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery.

Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran

Proceedings of the 2011 IEEE International Test Conference, 2010

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS.

Fulvio Spagna, Lidong Chen, Mamatha Deshpande, Yongping Fan, Doug Gambetta, Sujatha Gowder, Sitaraman Iyer, Rohit Kumar, Peter Kwok, Renuka Krishnamurthy, Chien-chun Lin, Ravindran Mohanavelu, Roan Nicholson, Jeff Ou, Marcus Pasquarella, Kavitha Prasad, Hendra Rustam, Luke Tong, Amanda Tran, John Wu, Xuguang Zhang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS.

Lidong Chen, Xuguang Zhang, Fulvio Spagna

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2001

An improved delay compensation technique for digital clock recovery loops.

Fulvio Spagna

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Phase Locked Loop Using Delay Compensation Techniques.

Fulvio Spagna

Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 2000