Yongping Fan

According to our database1, Yongping Fan authored at least 5 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2016
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2010
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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