G. Fraidy Bouesse

According to our database, G. Fraidy Bouesse authored at least 6 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2006

Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.

G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin

Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005

Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.

G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

A clock-less low-voltage AES crypto-processor.

G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain

Proceedings of the 31st European Solid-State Circuits Conference, 2005

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.

G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain

Proceedings of the 2005 Design, 2005

2004

High Security Smartcards.

Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain

Proceedings of the 2004 Design, 2004

2003

Statistic Implementation of QDI Asynchronous Primitives.

Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin

Proceedings of the Integrated Circuit and System Design, 2003