Marc Renaudin
According to our database1,
Marc Renaudin
authored at least 102 papers
between 1989 and 2020.
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Bibliography
2020
Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks.
Proceedings of the 4th Workshop on Models for Formal Analysis of Real Systems, 2020
2018
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI.
J. Low Power Electron., 2018
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
2014
Signal Process., 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
2013
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools.
Proceedings of the Design, Automation and Test in Europe, 2013
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
ACM Trans. Design Autom. Electr. Syst., 2011
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.
J. Cryptol., 2011
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
CoRR, 2011
2010
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies.
Microelectron. Reliab., 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.
Proceedings of the 15th European Test Symposium, 2010
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
EURASIP J. Adv. Signal Process., 2009
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
J. Electr. Comput. Eng., 2008
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Tech. Sci. Informatiques, 2007
IEEE Trans. Parallel Distributed Syst., 2007
A new analytical approach of the impact of jitter on continuous time delta sigma converters.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Proceedings of the Fourth Annual IEEE Communications Society Conference on Sensor, 2007
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.
IEEE Trans. Computers, 2006
On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits.
J. Low Power Electron., 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006
Proceedings of the 14th European Signal Processing Conference, 2006
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Asynchronous Systems on Programmable Logic.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Challenges in Ad Hoc Networking, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator.
Proceedings of the 2005 joint conference on Smart objects and ambient intelligence, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2004
Microelectron. J., 2004
La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués.
Ann. des Télécommunications, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
Validation of asynchronous circuit specifications using IF/CADP.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.
Proceedings of the 2002 Design, 2002
2001
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller.
IEEE J. Solid State Circuits, 2001
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
1999
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
1997
Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective.
Int. J. Pattern Recognit. Artif. Intell., 1997
1996
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider.
IEEE J. Solid State Circuits, 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Microprocess. Microprogramming, 1993
A general time domain approach for the design of perfect reconstruction modulated filter banks.
Proceedings of the IEEE International Conference on Acoustics, 1993
Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms.
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989