Philippe Maurine

According to our database1, Philippe Maurine authored at least 117 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
From theory to practice: horizontal attacks on protected implementations of modular exponentiations.
J. Cryptographic Engineering, 2019

Electromagnetic Fault Injection : How Faults Occur.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

Breaking Mobile Firmware Encryption through Near-Field Side-Channel Analysis.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
Estimating the Signal-to-Noise Ratio Under Repeated Sampling of the Same Centered Signal: Applications to Side-Channel Attacks on a Cryptoprocessor.
IEEE Trans. Information Theory, 2018

Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits.
Proceedings of the 2018 International Symposium on Physical Design, 2018

The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Thermal Scans for Detecting Hardware Trojans.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018

Electromagnetic Activity vs. Logical Activity: Near Field Scans for Reverse Engineering.
Proceedings of the Smart Card Research and Advanced Applications, 2018

2017
An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification.
IEEE Trans. VLSI Syst., 2017

Method for evaluation of transient-fault detection techniques.
Microelectronics Reliability, 2017

Electromagnetic fault injection: the curse of flip-flops.
J. Cryptographic Engineering, 2017

Mutual information analysis: higher-order statistical moments, efficiency and efficacy.
J. Cryptographic Engineering, 2017

Importance of IR drops on the modeling of laser-induced transient faults.
Proceedings of the 14th International Conference on Synthesis, 2017

Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Impacts of Technology Trends on Physical Attacks?
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

An EM Fault Injection Susceptibility Criterion and Its Application to the Localization of Hotspots.
Proceedings of the Smart Card Research and Advanced Applications, 2017

2016
Granularity and detection capability of an adaptive embedded Hardware Trojan detection system.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Body Biasing Injection Attacks in Practice.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016

An Embedded Digital Sensor against EM and BB Fault Injection.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

On-chip fingerprinting of IC topology for integrity verification.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fully-digital EM pulse detector.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Vertical and horizontal correlation attacks on RNS-based exponentiations.
J. Cryptographic Engineering, 2015

Extraction of intrinsic structure for Hardware Trojan detection.
IACR Cryptology ePrint Archive, 2015

Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Interest of MIA in frequency domain?
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015

EM Injection: Fault Model and Locality.
Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2015

Collision Based Attacks in Practice.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Collision for Estimating SCA Measurement Quality and Related Applications.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures.
IEEE Trans. on Circuits and Systems, 2014

A model of the leakage in the frequency domain and its application to CPA and DPA.
J. Cryptographic Engineering, 2014

Analysis Of Variance and CPA in SCA.
IACR Cryptology ePrint Archive, 2014

Electromagnetic analysis and fault injection onto secure circuits.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI).
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A frequency leakage model for SCA.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Efficiency of a glitch detector against electromagnetic fault injection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Attacking Randomized Exponentiations Using Unsupervised Learning.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

On Adaptive Bandwidth Selection for Efficient MIA.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

Evidence of a Larger EM-Induced Fault Model.
Proceedings of the Smart Card Research and Advanced Applications, 2014

2013
A Frequency Leakage Model and its application to CPA and DPA.
IACR Cryptology ePrint Archive, 2013

Countermeasures against EM analysis for a secured FPGA-based AES implementation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

An evaluation of an AES implementation protected against EM analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Voltage Spikes on the Substrate to Obtain Timing Faults.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Electromagnetic Analysis on RSA Algorithm Based on RNS.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2013

2012
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence.
IEEE Trans. VLSI Syst., 2012

Delay-correlation-aware SSTA based on conditional moments.
Microelectronics Journal, 2012

Secure D flip-flop against side channel attacks.
IET Circuits, Devices & Systems, 2012

Magnitude Squared Coherence based SCA.
IACR Cryptology ePrint Archive, 2012

Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system-.
IACR Cryptology ePrint Archive, 2012

Statistical timing characterization.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Techniques for EM Fault Injection: Equipments and Experimental Results.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

Amplitude demodulation-based EM analysis of different RSA implementations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Embedding statistical tests for on-chip dynamic voltage and temperature monitoring.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

SCA with Magnitude Squared Coherence.
Proceedings of the Smart Card Research and Advanced Applications, 2012

Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests.
Proceedings of the IEEE International Conference on Control Applications, 2012

2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectronics Journal, 2011

Spectral Coherence Analysis - First Experimental Results -.
IACR Cryptology ePrint Archive, 2011

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.
IEEE Design & Test of Computers, 2011

A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Local and Direct EM Injection of Power Into CMOS Integrated Circuits.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

2010
On-Chip Process Variability Monitoring Flow.
J. Low Power Electronics, 2010

Spatial EM jamming: A countermeasure against EM Analysis?
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Modeling Time Domain Magnetic Emissions of ICs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Differential Power Analysis enhancement with statistical preprocessing.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Timing margin evaluation with a simple statistical timing analysis flow.
J. Embedded Computing, 2009

Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Interpreting SSTA Results with Correlation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Product On-Chip Process Compensation for Low Power and Yield Enhancement.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Editorial.
Integration, 2008

Evaluating the robustness of secure triple track logic through prototyping.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Triple Rail Logic Robustness against DPA.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

SSTA considering switching process induced correlations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Temperature- and Voltage-Aware Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Improvement of dual rail logic as a countermeasure against DPA.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Temperature and voltage aware timing analysis: application to voltage drops.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Logical effort model extension to propagation delay representation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
Integration, 2006

Security evaluation of dual rail logic against DPA attacks.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Statistical Characterization of Library Timing Performance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Timing analysis in presence of supply voltage and temperature variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Circuit sizing method under delay constraint.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Request-skip adders : CMOS standard cell data dependent adders.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Compact and Secured Primitives for the Design of Asynchronous Circuits.
J. Low Power Electronics, 2005

Speed Indicators for Circuit Optimization.
Proceedings of the Integrated Circuit and System Design, 2005

A Method to Design Compact Dual-rail Asynchronous Primitives.
Proceedings of the Integrated Circuit and System Design, 2005

Temperature Dependency in UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2005

Circuit optimization based on speed indicators.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Low Power Oriented CMOS Circuit Optimization Protocol.
Proceedings of the 2005 Design, 2005

2004
Performance Metric Based Optimization Protocol.
Proceedings of the Integrated Circuit and System Design, 2004

Physical Extension of the Logical Effort Model.
Proceedings of the Integrated Circuit and System Design, 2004

Temperature Dependence in Low Power CMOS UDSM Process.
Proceedings of the Integrated Circuit and System Design, 2004

Design Optimization with Automated Cell Generation.
Proceedings of the Integrated Circuit and System Design, 2004

Delay bound based CMOS gate sizing technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
CMOS Gate Sizing under Delay Constraint.
Proceedings of the Integrated Circuit and System Design, 2003

Metric Definition for Circuit Speed Optimization.
Proceedings of the Integrated Circuit and System Design, 2003

Statistic Implementation of QDI Asynchronous Primitives.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Transition time modeling in deep submicron CMOS.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Structure Independent Representation of Output Transition Time for CMOS Library.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Gate speed improvement at minimal power dissipation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Output transition time modeling of CMOS structures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Gate Sizing for Low Power Design.
Proceedings of the SOC Design Methodologies, 2001

Feasible Delay Bound Definition.
Proceedings of the SOC Design Methodologies, 2001

2000
Second Generation Delay Model for Submicron CMOS Process.
Proceedings of the Integrated Circuit Design, 2000

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design.
Proceedings of the Integrated Circuit Design, 2000


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