Philippe Maurine
Orcid: 0000-0002-9706-5710
According to our database1,
Philippe Maurine
authored at least 139 papers
between 2000 and 2023.
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Bibliography
2023
Spatial dependency analysis to extract information from side-channel mixtures: extended version.
J. Cryptogr. Eng., November, 2023
Revisiting Mutual Information Analysis: Multidimensionality, Neural Estimation and Optimality Proofs.
J. Cryptol., October, 2023
IEEE Trans. Computers, 2023
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2023
Proceedings of the Smart Card Research and Advanced Applications, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IACR Cryptol. ePrint Arch., 2022
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2022
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IACR Cryptol. ePrint Arch., 2021
Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probes.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Proceedings of the 18th Workshop on Fault Detection and Tolerance in Cryptography, 2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
Protecting Secure ICs Against Side-Channel Attacks by Identifying and Quantifying Potential EM and Leakage Hotspots at Simulation Stage.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021
2020
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the Applied Cryptography and Network Security Workshops, 2020
2019
From theory to practice: horizontal attacks on protected implementations of modular exponentiations.
J. Cryptogr. Eng., 2019
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
2018
Estimating the Signal-to-Noise Ratio Under Repeated Sampling of the Same Centered Signal: Applications to Side-Channel Attacks on a Cryptoprocessor.
IEEE Trans. Inf. Theory, 2018
Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits.
Proceedings of the 2018 International Symposium on Physical Design, 2018
The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018
Electromagnetic Activity vs. Logical Activity: Near Field Scans for Reverse Engineering.
Proceedings of the Smart Card Research and Advanced Applications, 2018
2017
An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Microelectron. Reliab., 2017
Mutual information analysis: higher-order statistical moments, efficiency and efficacy.
J. Cryptogr. Eng., 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation.
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
An EM Fault Injection Susceptibility Criterion and Its Application to the Localization of Hotspots.
Proceedings of the Smart Card Research and Advanced Applications, 2017
2016
Granularity and detection capability of an adaptive embedded Hardware Trojan detection system.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
J. Cryptogr. Eng., 2015
IACR Cryptol. ePrint Arch., 2015
Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015
Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the Smart Card Research and Advanced Applications, 2015
2014
Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
J. Cryptogr. Eng., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI).
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014
Proceedings of the Smart Card Research and Advanced Applications, 2014
2013
IACR Cryptol. ePrint Arch., 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks.
Proceedings of the Smart Card Research and Advanced Applications, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system-.
IACR Cryptol. ePrint Arch., 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
Proceedings of the Smart Card Research and Advanced Applications, 2012
Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests.
Proceedings of the IEEE International Conference on Control Applications, 2012
2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectron. J., 2011
IACR Cryptol. ePrint Arch., 2011
IEEE Des. Test Comput., 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
J. Embed. Comput., 2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects.
Integr., 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
J. Low Power Electron., 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 2005 Design, 2005
2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Delay bound based CMOS gate sizing technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Gate Sizing for Low Power Design.
Proceedings of the SOC Design Methodologies, 2001
Feasible Delay Bound Definition.
Proceedings of the SOC Design Methodologies, 2001
2000
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the Integrated Circuit Design, 2000