Gang Wu

Affiliations:
  • Synopsys, Inc., Hillsboro, OR, USA
  • Iowa State University, Department of Electrical and Computer Engineering, Ames, IA, USA (PhD)


According to our database1, Gang Wu authored at least 8 papers between 2014 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Online presence:

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Bibliography

2017
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A Fast Incremental Cycle Ratio Algorithm.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Flip-flop clustering by weighted K-means algorithm.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
POLAR 3.0: An Ultrafast Global Placement Engine.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Asynchronous circuit placement by lagrangian relaxation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014


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