Peter A. Beerel
Orcid: 0000-0002-8283-0168
According to our database1,
Peter A. Beerel
authored at least 196 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
AFLoRA: Adaptive Freezing of Low Rank Adaptation in Parameter Efficient Fine-Tuning of Large Models.
CoRR, 2024
Toward High Performance, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ.
CoRR, 2024
CoRR, 2024
A Novel Optimization Algorithm for Buffer and Splitter Minimization in Phase-Skipping Adiabatic Quantum-Flux-Parametron Circuits.
CoRR, 2024
An Efficient and Scalable Clocking Assignment Algorithm for Multi-Threaded Multi-Phase Single Flux Quantum Circuits.
CoRR, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors.
Frontiers Neuroinformatics, March, 2023
When Bio-Inspired Computing meets Deep Learning: Low-Latency, Accurate, & Energy-Efficient Spiking Neural Networks from Artificial Neural Networks.
CoRR, 2023
Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology.
CoRR, 2023
Let's Roll: Synthetic Dataset Analysis for Pedestrian Detection Across Different Shutter Types.
CoRR, 2023
Mitigate Replication and Copying in Diffusion Models with Generalized Caption and Dual Fusion Enhancement.
CoRR, 2023
CoRR, 2023
FLOAT: Fast Learnable Once-for-All Adversarial Training for Tunable Trade-off between Accuracy and Robustness.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Bridging the Gap Between Spiking Neural Networks & LSTMs for Latency & Energy Efficiency.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design Considerations for 3D Heterogeneous Integration Driven Analog Processing-in-Pixel for Extreme-Edge Intelligence.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023
Learning to Linearize Deep Neural Networks for Secure and Efficient Private Inference.
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
SAL-ViT: Towards Latency Efficient Private Inference on ViT using Selective Attention Search with a Learnable Softmax Approximation.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
RNA-ViT: Reduced-Dimension Approximate Normalized Attention Vision Transformers for Latency Efficient Private Inference.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Quantpipe: Applying Adaptive Post-Training Quantization For Distributed Transformer Pipelines In Dynamic Edge Environments.
Proceedings of the IEEE International Conference on Acoustics, 2023
Sparse Mixture Once-for-all Adversarial Training for Efficient in-situ Trade-off between Accuracy and Robustness of DNNs.
Proceedings of the IEEE International Conference on Acoustics, 2023
In-Sensor & Neuromorphic Computing Are all You Need for Energy Efficient Computer Vision.
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
C<sup>2</sup>PI: An Efficient Crypto-Clear Two-Party Neural Network Private Inference.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Making Models Shallow Again: Jointly Learning to Reduce Non-Linearity and Depth for Latency-Efficient Private Inference.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2022
Toward Adversary-aware Non-iterative Model Pruning through Dynamic Network Rewiring of DNNs.
ACM Trans. Embed. Comput. Syst., September, 2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CoRR, 2022
A Fast and Efficient Conditional Learning for Tunable Trade-Off between Accuracy and Robustness.
CoRR, 2022
P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications.
CoRR, 2022
P<sup>2</sup>M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the Computer Vision - ECCV 2022 Workshops, 2022
PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits.
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Deep-n-Cheap: An Automated Efficient and Extensible Search Framework for Cost-Effective Deep Learning.
SN Comput. Sci., 2021
CoRR, 2021
HYPER-SNN: Towards Energy-efficient Quantized Deep Spiking Neural Networks for Hyperspectral Image Classification.
CoRR, 2021
Spike-Thrift: Towards Energy-Efficient Deep Spiking Neural Networks by Limiting Spiking Activity via Attention-Guided Compression.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Training Energy-Efficient Deep Spiking Neural Networks with Single-Spike Hybrid Input Encoding.
Proceedings of the International Joint Conference on Neural Networks, 2021
HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures.
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
IEEE Trans. Computers, 2020
CoRR, 2020
Modeling and Characterization of Metastability in Single Flux Quantum (SFQ) Synchronizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
Proceedings of The 12th Asian Conference on Machine Learning, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133).
NII Shonan Meet. Rep., 2019
IET Comput. Digit. Tech., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the 2019 IEEE Cybersecurity Development, 2019
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 57th Annual Allerton Conference on Communication, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.
CoRR, 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 2018 Information Theory and Applications Workshop, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 9th International Conference on Computing, 2018
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2017, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016
Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016
2015
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
TDTB error detecting latches: Timing violation sensitivity analysis and optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014
2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces.
Proceedings of the 33th Communicating Process Architectures Conference, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment.
Proceedings of the Concurrency, 2010
2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2007
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007
2006
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 28th Communicating Process Architectures Conference, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002
2001
IEEE J. Sel. Areas Commun., 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
Implicit enumeration of strongly connected components and anapplication to formal verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the Correct Hardware Design and Verification Methods, 1999
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver.
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Formal Methods Syst. Des., 1998
Computer engineering using innovative instructional technologies at the University of Southern California.
Proceedings of the 1998 workshop on Computer architecture education, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
1997
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking.
Integr., 1997
Proceedings of the 34st Conference on Design Automation, 1997
Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits.
Proceedings of the conference on European design automation, 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995
1994
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
1991
Proceedings of the 28th Design Automation Conference, 1991