Peter A. Beerel

According to our database1, Peter A. Beerel authored at least 155 papers between 1991 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Towards a Formal Treatment of Logic Locking.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Fast and Efficient Conditional Learning for Tunable Trade-Off between Accuracy and Robustness.
CoRR, 2022

Toward Efficient Hyperspectral Image Processing inside Camera Pixels.
CoRR, 2022

P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications.
CoRR, 2022

Radiation Hardening by Design Techniques for the Mutual Exclusion Element.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits.
ACM Trans. Design Autom. Electr. Syst., 2021

Metastability in Superconducting Single Flux Quantum (SFQ) Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Deep-n-Cheap: An Automated Efficient and Extensible Search Framework for Cost-Effective Deep Learning.
SN Comput. Sci., 2021

Pipeline Parallelism for Inference on Heterogeneous Edge Computing.
CoRR, 2021

Towards Low-Latency Energy-Efficient Deep SNNs via Attention-Guided Compression.
CoRR, 2021

HYPER-SNN: Towards Energy-efficient Quantized Deep Spiking Neural Networks for Hyperspectral Image Classification.
CoRR, 2021

GF-Flush: A GF(2) Algebraic Attack on Secure Scan Chains.
CoRR, 2021

Spike-Thrift: Towards Energy-Efficient Deep Spiking Neural Networks by Limiting Spiking Activity via Attention-Guided Compression.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021

Analyzing the Confidentiality of Undistillable Teachers in Knowledge Distillation.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Training Energy-Efficient Deep Spiking Neural Networks with Single-Spike Hybrid Input Encoding.
Proceedings of the International Joint Conference on Neural Networks, 2021

HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures.
ACM Trans. Design Autom. Electr. Syst., 2020

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Pre-Defined Sparsity for Low-Complexity Convolutional Neural Networks.
IEEE Trans. Computers, 2020

A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.
CoRR, 2020

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit.
CoRR, 2020

Modeling and Characterization of Metastability in Single Flux Quantum (SFQ) Synchronizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Neural Network Training with Approximate Logarithmic Computations.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Formal Verification of Flow Equivalence in Desynchronized Designs.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning.
Proceedings of The 12th Asian Conference on Machine Learning, 2020

2019
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133).
NII Shonan Meet. Rep., 2019

Yield modelling and analysis of bundled data and ring-oscillator based designs.
IET Comput. Digit. Tech., 2019

Pre-Defined Sparse Neural Networks With Hardware Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Metastability-Resilient Synchronization FIFO for SFQ Logic.
CoRR, 2019

A Pre-defined Sparse Kernel Based Convolution for Deep CNNs.
CoRR, 2019

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs.
CoRR, 2019

System-Level Framework for Logic Obfuscation with Quantified Metrics for Evaluation.
Proceedings of the 2019 IEEE Cybersecurity Development, 2019

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

pSConv: A Pre-defined S parse Kernel Based Convolution for Deep CNNs.
Proceedings of the 57th Annual Allerton Conference on Communication, 2019

2018
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Area Optimization of Timing Resilient Designs Using Resynthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.
CoRR, 2018

A Highly Parallel FPGA Implementation of Sparse Neural Network Training.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Characterizing Sparse Connectivity Patterns in Neural Networks.
Proceedings of the 2018 Information Theory and Applications Workshop, 2018

A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Opportunities for Machine Learning in Electronic Design Automation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Morse Code Datasets for Machine Learning.
Proceedings of the 9th International Conference on Computing, 2018

Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Accelerating Training of Deep Neural Networks via Sparse Edge Processing.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2017, 2017

Retiming of Two-Phase Latch-Based Resilient Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Interleaver design for deep neural networks.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Testable MUTEX Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2016

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Area optimization of resilient designs guided by a mixed integer geometric program.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

TDTB error detecting latches: Timing violation sensitivity analysis and optimization.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A path towards average-case silicon via asynchronous resilient bundled-data design.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Logical equivalence checking of asynchronous circuits using commercial tools.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Design and Analysis of Testable Mutual Exclusion Elements.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Blade - A Timing Violation Resilient Asynchronous Template.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Performance Optimization and Analysis of Blade Designs under Delay Variability.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Performance-Driven Clustering of Asynchronous Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Asynchronous circuit placement by lagrangian relaxation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Stochastic analysis of Bubble Razor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

Reconditioning: Automatic Power Optimization of QDI Circuits.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Slack matching mode-based asynchronous circuits for average-case performance.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

A polynomial time flow for implementing free-choice Petri-nets.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Energy and Performance Models for Synchronous and Asynchronous Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Proteus: An ASIC Flow for GHz Asynchronous Designs.
IEEE Des. Test Comput., 2011

SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces.
Proceedings of the 33th Communicating Process Architectures Conference, 2011

An area-efficient multi-level single-track pipeline template.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment.
Proceedings of the Concurrency, 2010

2009
Crosstalk in High-Performance Asynchronous Designs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2007
Low Power and Energy Efficient Asynchronous Design.
J. Low Power Electron., 2007

Design of a High-Speed Asynchronous Turbo Decoder.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

High performance asynchronous design using single-track full-buffer standard cells.
IEEE J. Solid State Circuits, 2006

Back-Annotation in High-Speed Asynchronous Design.
J. Low Power Electron., 2006

Asynchronous Design for High-Speed and Low-Power Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

High-Performance Noise-Robust Asynchronous Circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Slack Matching Asynchronous Designs.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

High-level Synthesis for Highly Concurrent Hardware Systems.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2005

High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog.
Proceedings of the 28th Communicating Process Architectures Conference, 2005

2004
Bridging the Gap between Asynchronous Design and Designers.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A memory allocation and assignment method using multiway partitioning.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Voltage-pulse driven harmonic resonant rail drivers for low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 2003

An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Reducing probabilistic timed petri nets for asynchronous architectural analysis.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Asynchronous Circuits: An Increasingly Practical Design Solution (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Control Circuit Templates for Asynchronous Bundled-Data Pipelines.
Proceedings of the 2002 Design, 2002

High-Speed Non-Linear Asynchronous Pipelines.
Proceedings of the 2002 Design, 2002

Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.
Proceedings of the 2002 Design, 2002

High-Speed QDI Asynchronous Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Relative Timing Based Verification of Timed Circuits and Systems.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Performance Analysis of Asynchronous Circuits Using Markov Chains.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001
An asynchronous instruction length decoder.
IEEE J. Solid State Circuits, 2001

A low latency SISO with application to broadband turbo decoding.
IEEE J. Sel. Areas Commun., 2001

Theory and practical implementation of harmonic resonant rail driver.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Implicit enumeration of strongly connected components and anapplication to formal verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Sibling-substitution-based BDD minimization using don't cares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An asynchronous matrix-vector multiplier for discrete cosine transform.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Accelerating Markovian analysis of asynchronous systems using state compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Average-case technology mapping of asynchronous burst-mode circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Statistically optimized asynchronous barrel shifters for variable length codecs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Implicit enumeration of strongly connected components.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares.
Proceedings of the 1999 Design, 1999

Hazard-Freedom Checking in Speed-Independent Systems.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

RAPPID: An Asynchronous Instruction Length Decoder.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Efficient state classification of finite-state Markov chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Covering conditions and algorithms for the synthesis of speed-independent circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Checking Combinational Equivalence of Speed-Independent Circuits.
Formal Methods Syst. Des., 1998

Computer engineering using innovative instructional technologies at the University of Southern California.
Proceedings of the 1998 workshop on Computer architecture education, 1998

Don't Care-Based BDD Minimization for Embedded Software.
Proceedings of the 35th Conference on Design Automation, 1998

Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking.
Integr., 1997

Safe BDD Minimization Using Don't Cares.
Proceedings of the 34st Conference on Design Automation, 1997

Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Estimation of energy consumption in speed-independent control circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits.
Proceedings of the conference on European design automation, 1996

High-performance asynchronous pipeline circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

Optimizing average-case delay in technology mapping of burst-mode circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Estimation and bounding of energy consumption in burst-mode control circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Technology mapping of timed circuits.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994
Sufficient conditions for correct gate-level speed-independent circuits.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Efficient verification of determinate speed-independent circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Semi-modularity and testability of speed-independent circuits.
Integr., 1992

Automatic gate-level synthesis of speed-independent circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Testability of Asynchronous Timed Control Circuits with Delay Assumptions.
Proceedings of the 28th Design Automation Conference, 1991


  Loading...