Gaurav Kumar

Orcid: 0000-0002-2357-6382

Affiliations:
  • Indian Institute of Technology Jammu, Department of Electrical Engineering, Jammu, India


According to our database1, Gaurav Kumar authored at least 24 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Secure and scalable access protocol for enhancing IEEE 1687 network security.
Cybersecur., December, 2026

On Enhancing the Security of Streaming Scan Network through Dual-Functional TDR.
ACM Trans. Design Autom. Electr. Syst., March, 2026

A New Scan Based Attack on AES With Plaintext Restriction Countermeasure.
IEEE Trans. Emerg. Top. Comput., 2026

Round key attack: Exploiting AES round key generation reversibility through scan analysis.
J. Inf. Secur. Appl., 2026

SRAM PUF-based logic locking framework for IoT authentication and IP protection.
Comput. Electr. Eng., 2026

On Evaluating the Security of Complete Access Protocol of IJTAG Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory.
ACM Trans. Embed. Comput. Syst., 2025

On Enhancing the Security Against Memory Disclosure Attacks.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

Poster Abstract: SRAM PUF-Based Logic Locking for Secure Authentication and IP Protection.
Proceedings of the 23rd ACM Conference on Embedded Networked Sensor Systems, 2025

A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Approximating Nonlinear Activation Function Using Genetic Programming.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
On Exploring Non-negative Matrix Factorization for Deep Neural Network Compression.
Proceedings of the 21st International SoC Design Conference, 2024

On Evaluating Test Response Obfuscation and Encryption Countermeasures.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

2023
Enhancing the Security of IJTAG Network Using Inherently Secure SIB.
Proceedings of the VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence, 2023

On Protecting IJTAG using an Inherently Secure SIB.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

On Evaluating the Security of Dynamic Scan Obfuscation Scheme.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

On Enhancing the Security of Streaming Scan Network Architecture.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Power Analysis Attack on Locking SIB based IJTAG Achitecture.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Low Cost Implementation of Deep Neural Network on Hardware.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

On Protecting IJTAG from Data Sniffing and Alteration Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

On Attacking IJTAG Architecture based on Locking SIB with Security LFSR.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

On Attacking Locking SIB based IJTAG Architecture.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A New Access Protocol for Elevating the Security of IJTAG Network.
Proceedings of the IEEE 31st Asian Test Symposium, 2022


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