Satyadev Ahlawat

According to our database, Satyadev Ahlawat authored at least 28 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

MisGUIDE : Defense Against Data-Free Deep Learning Model Extraction.

Mahendra Gurve, Sankar Behera, Satyadev Ahlawat, Yamuna Prasad

CoRR, 2024

2023

On Protecting IJTAG using an Inherently Secure SIB.

Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm.

Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh

Proceedings of the IEEE International Conference on Service-Oriented System Engineering, 2023

On Evaluating the Security of Dynamic Scan Obfuscation Scheme.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

On Enhancing the Security of Streaming Scan Network Architecture.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

Power Analysis Attack on Locking SIB based IJTAG Achitecture.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Low Cost Implementation of Deep Neural Network on Hardware.

Gaurav Kumar, Anuj Kumar, Satyadev Ahlawat, Yamuna Prasad

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

On Protecting IJTAG from Data Sniffing and Alteration Attacks.

Anjum Riaz, Gaurav Kumar, Jaynarayan T. Tudu, Satyadev Ahlawat

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

On Attacking IJTAG Architecture based on Locking SIB with Security LFSR.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

On Attacking Locking SIB based IJTAG Architecture.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Evaluating Security of New Locking SIB-based Architectures.

Yogendra Sao, Anjum Riaz, Satyadev Ahlawat, Sk Subidh Ali

Proceedings of the IEEE European Test Symposium, 2022

A New Access Protocol for Elevating the Security of IJTAG Network.

Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

A Framework for Configurable Joint-Scan Design-for-Test Architecture.

Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh

J. Electron. Test., 2021

2019

Securing Scan through Plain-text Restriction.

Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Preventing Scan Attack through Test Response Encryption.

Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

On Securing Scan Design Through Test Vector Encryption.

Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

In-situ Monitoring for Slack Time Violation Without Performance Penalty.

Nihar Hage, Satyadev Ahlawat, Virendra Singh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks.

Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

A Cost Effective Technique for Diagnosis of Scan Chain Faults.

Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A low cost technique for scan chain diagnosis.

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient test technique to prevent scan-based side-channel attacks.

Satyadev Ahlawat, Darshit Vaghani, Virendra Singh

Proceedings of the 22nd IEEE European Test Symposium, 2017

Preventing scan-based side-channel attacks through key masking.

Satyadev Ahlawat, Darshit Vaghani, Virendra Singh

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

On Securing Scan Design from Scan-Based Side-Channel Attacks.

Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Guided shifting of test pattern to minimize test time in serial scan.

Jaynarayan T. Tudu, Satyadev Ahlawat

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

On minimization of test power through modified scan flip-flop.

Satyadev Ahlawat, Jaynarayan T. Tudu

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A high performance scan flip-flop design for serial and mixed mode scan test.

Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Enabling LOS delay test with slow scan enable.

Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan.

Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh

Proceedings of the 24th IEEE Asian Test Symposium, 2015