Geraldine Shirley

According to our database1, Geraldine Shirley authored at least 8 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.
Cryptogr., September, 2023

2022
Dynamic Key Updates for LUT Locked Design.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic.
J. Hardw. Syst. Secur., 2021

A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Multilayer Camouflaged Secure Boot for SoCs.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

Secure Design Flow of FPGA Based RISC-V Implementation.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019


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