James F. Plusquellic

Orcid: 0000-0002-1876-117X

Affiliations:
  • University of New Mexico, Albuquerque, USA


According to our database1, James F. Plusquellic authored at least 110 papers between 1996 and 2023.

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Bibliography

2023
Correction to: An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions.
J. Hardw. Syst. Secur., December, 2023

An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions.
J. Hardw. Syst. Secur., December, 2023

Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF.
IEEE Trans. Emerg. Top. Comput., 2023

SAFE: Secure Symbiotic Positioning, Navigation, and Timing.
Proceedings of the IEEE Global Communications Conference, 2023

2022
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Local Trust in Internet of Things Based on Contract Theory.
Sensors, 2022

Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst., 2022

Enhancing Privacy in PUF-Cash through Multiple Trusted Third Parties and Reinforcement Learning.
ACM J. Emerg. Technol. Comput. Syst., 2022

Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA.
Cryptogr., 2022

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor.
Cryptogr., 2022

Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing.
CoRR, 2022

Orchestration of Reconfigurable Intelligent Surfaces for Positioning, Navigation, and Timing.
Proceedings of the IEEE Military Communications Conference, 2022

Reconfigurable Intelligent Surfaces enabling Positioning, Navigation, and Timing Services.
Proceedings of the IEEE International Conference on Communications, 2022

True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Network Economics-based Crowdsourcing in UAV-assisted Smart Cities Environments.
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022

2021
Secure LoRa Firmware Update with Adaptive Data Rate Techniques.
Sensors, 2021

Artificially Intelligent Electronic Money.
IEEE Consumer Electron. Mag., 2021

2020
NotchPUF: Printed Circuit Board PUF Based on Microstrip Notch Filter.
Cryptogr., 2020

Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity.
Cryptogr., 2020

Reinforcement Learning Toward Decision-Making for Multiple Trusted-Third-Parties in PUF-Cash.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Adaptive Data Rate Techniques for Energy Constrained Ad Hoc LoRa Networks.
Proceedings of the 2020 Global Internet of Things Summit, 2020

UAV-enabled Human Internet of Things.
Proceedings of the 16th International Conference on Distributed Computing in Sensor Systems, 2020

Analysis of IoT Authentication Over LoRa.
Proceedings of the 16th International Conference on Distributed Computing in Sensor Systems, 2020

Secure Energy Constrained LoRa Mesh Network.
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks, 2020

2019
Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash).
Cryptogr., 2019

Multilayer Camouflaged Secure Boot for SoCs.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

Secure Design Flow of FPGA Based RISC-V Implementation.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future.
Proceedings of the IEEE International Test Conference, 2019

2018
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Correlation-Based Robust Authentication (Cobra) Using Helper Data Only.
Cryptogr., 2018

An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays.
Cryptogr., 2018

Hardware Assisted Security Architecture for Smart Grid.
Proceedings of the IECON 2018, 2018

Self-authenticating secure boot for FPGAs.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Delay model and machine learning exploration of a hardware-embedded delay PUF.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
A Privacy-Preserving, Mutual PUF-Based Authentication Protocol.
Cryptogr., 2017

Leveraging Distributions in Physical Unclonable Functions.
Cryptogr., 2017

Analysis of Entropy in a Hardware-Embedded Delay PUF.
Cryptogr., 2017

Secure communication over CANBus.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Secure intra-vehicular communication over CANFD.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Poster: Hardware based security enhanced framework for automotives.
Proceedings of the 2016 IEEE Vehicular Networking Conference, 2016

On detecting delay anomalies introduced by hardware trojans.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Current based PUF exploiting random variations in SRAM cells.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF).
IEEE Trans. Computers, 2015

PUF-Based Authentication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Cyber-physical systems: A security perspective.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
ASIC implementation of a hardware-embedded physical unclonable function.
IET Comput. Digit. Tech., 2014

A non-volatile memory based physically unclonable function without helper data.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

IP-level implementation of a resistance-based physical unclonable function.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.
IEEE Des. Test, 2013

HELP: A Hardware-Embedded Delay PUF.
IEEE Des. Test, 2013

Secure mobile authentication and device association with enhanced cryptographic engines.
Proceedings of the 2013 International Conference on Privacy and Security in Mobile Systems, 2013

Stability analysis of a physical unclonable function based on metal resistance variations.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Securing Trusted Execution Environments with PUF Generated Secret Keys.
Proceedings of the 11th IEEE International Conference on Trust, 2012

Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

2011
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities.
IEEE Trans. Inf. Forensics Secur., 2011

Measuring within-die spatial variation profile through power supply current measurements.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect.
Proceedings of the 48th Design Automation Conference, 2011

2010
A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad I<sub>DDQ</sub> s.
IEEE Trans. Inf. Forensics Secur., 2010

A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits.
Proceedings of the 2010 IEEE International Workshop on Information Forensics and Security, 2010

Leveraging existing power control circuits and power delivery architecture for variability measurement.
Proceedings of the 2011 IEEE International Test Conference, 2010

Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system.
Proceedings of the 47th Design Automation Conference, 2010

2009
A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals.
J. Electron. Test., 2009

Characterizing within-die variation from multiple supply port IDDQ measurements.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

A physical unclonable function defined using power distribution system equivalent resistance variations.
Proceedings of the 46th Design Automation Conference, 2009

2008
Power supply signal calibration techniques for improving detection resolution to hardware Trojans.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Securing Designs against Scan-Based Side-Channel Attacks.
IEEE Trans. Dependable Secur. Comput., 2007

2006
Defect Simulation Methodology for i<sub>DDT</sub> Testing.
J. Electron. Test., 2006

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.
IEEE Des. Test Comput., 2006

A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005
A Comparitive Study of W-cdma Cell Search Designs.
J. Circuits Syst. Comput., 2005

Defect Detection Using Quiescent Signal Analysis.
J. Electron. Test., 2005

At-Speed Transition Fault Testing With Low Speed Scan Enable.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Securing Scan Design Using Lock and Key Technique.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Fault Simulation Model for i{DDT} Testing: An Investigation.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Power supply transient signal analysis for defect-oriented test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids.
J. Electron. Test., 2003

IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping.
Comput. Networks, 2003

Impedance Profile of a Commercial Power Grid and Test System.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

FPGA implementation of a fast Hadamard transformer for WCDMA.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Comparison of Branching CORDIC Implementations.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001
IC Diagnosis Using Multiple Supply Pad IDDQs.
IEEE Des. Test Comput., 2001

A Process and Technology-Tolerant IDDQ Method for IC Diagnosis.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Detecting delay faults using power supply transient signal analysis.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Power supply transient signal integration circuit.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Detection of CMOS Defects under Variable Processing Conditions.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Predicting device performance from pass/fail transient signal analysis data.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Defect detection using power supply transient signal analysis.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
Characterization of CMOS Defects using Transient Signal Analysis.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Digital Integrated Circuit Testing using Transient Signal Analysis.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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