Gereon Führ

Orcid: 0000-0003-1321-8458

According to our database1, Gereon Führ authored at least 11 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs.
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA.
Integr., 2019

Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs.
IEEE Embed. Syst. Lett., 2019

A heuristic for multi objective software application mappings on heterogeneous MPSoCs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Combined MPSoC Task Mapping and Memory Optimization for Low-Power.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

2017
DVFS-enabled power-performance trade-off in MPSoC SW application mapping.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model.
ACM Trans. Embed. Comput. Syst., 2016

Black box ESL power estimation for loosely-timed TLM models.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Black box power estimation for digital signal processors using virtual platforms.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

2015
ESL power estimation using virtual platforms with black box processor models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015


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