Rainer Leupers
Orcid: 0000-0002-6735-3033Affiliations:
- RWTH Aachen University, Germany
According to our database1,
Rainer Leupers
authored at least 307 papers
between 1993 and 2024.
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Bibliography
2024
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL.
CoRR, 2024
CoRR, 2024
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024
2023
J. Syst. Archit., February, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Frequency and noise characterization for baseband signal processing on neuromorphic circuits.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
"S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar Arrays.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
2022
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Int. J. Parallel Program., 2022
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security.
IEEE Des. Test, 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs.
IEEE Open J. Circuits Syst., 2021
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.
ACM J. Emerg. Technol. Comput. Syst., 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling.
Integr., 2020
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect.
CoRR, 2020
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit.
IEEE Access, 2020
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables.
Proceedings of the 31st IEEE International Symposium on Software Reliability Engineering, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020
2019
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA.
Integr., 2019
IEEE Embed. Syst. Lett., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the International Conference on Computing, Networking and Communications, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
A heuristic for multi objective software application mappings on heterogeneous MPSoCs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR, 2018
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018
Proceedings of the Smart Cities, Green Technologies and Intelligent Transport Systems, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach.
Proceedings of the 2018 IEEE International Conference on Vehicular Electronics and Safety, 2018
Proceedings of the 2018 International Conference on Computing, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Int. J. Parallel Program., 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017
Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017
VLSI implementation of LS-SVM training and classification using entropy based subset-selection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition.
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 International Conference on Compilers, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model.
ACM Trans. Embed. Comput. Syst., 2016
MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs.
ACM Trans. Embed. Comput. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
J. Syst. Archit., 2016
J. Syst. Archit., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Automatic recognition of computational kernels for platform-dependent code optimizations.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Reconfigurable Technol. Syst., 2015
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
A comparative investigation of device-specific mechanisms for exploiting HPC accelerators.
Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the Beyond Databases, Architectures and Structures, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Improving ESL power models using switching activity information from timed functional models.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014
Pre-architectural performance estimation for ASIP design based on abstract processor models.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014
A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture.
Proceedings of the IEEE International Conference on Communications, 2014
VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A flexible ASIP architecture for connected components labeling in embedded vision applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
IEEE Trans. Ind. Informatics, 2013
Int. J. Embed. Real Time Commun. Syst., 2013
IEEE Des. Test, 2013
EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment
CoRR, 2013
DSPACE hardware architecture for on-board real-time image/video processing in European space missions.
Proceedings of the Real-Time Image and Video Processing 2013, 2013
Proceedings of the ISWCS 2013, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013
Creation of ESL power models for communication architectures using automatic calibration.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013
2012
Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Softw. Pract. Exp., 2011
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
Int. J. Embed. Real Time Commun. Syst., 2011
Int. J. Embed. Real Time Commun. Syst., 2011
Des. Autom. Embed. Syst., 2011
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Int. J. Parallel Program., 2010
Int. J. Embed. Real Time Commun. Syst., 2010
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of IEEE International Conference on Communications, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
ACM Trans. Archit. Code Optim., 2009
Microelectron. J., 2009
IACR Cryptol. ePrint Arch., 2009
CoRR, 2009
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations.
Proceedings of the Third IEEE International Conference on Secure Software Integration and Reliability Improvement, 2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embed. Comput. Syst., 2008
J. Comput., 2008
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
Int. J. Embed. Syst., 2008
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
Int. J. Embed. Syst., 2008
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
ACM Trans. Embed. Comput. Syst., 2007
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the 2007 International Conference on Compilers, 2007
Kluwer, ISBN: 978-1-4020-5685-7, 2007
2006
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
J. VLSI Signal Process., 2006
ACM Trans. Embed. Comput. Syst., 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
An interprocedural code optimization technique for network processors using hardware multi-threading support.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A design flow for configurable embedded processors based on optimized instruction set extension synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Integrated system-level modeling of network-on-chip enabled multi-processor platforms.
Kluwer, ISBN: 978-1-4020-4825-8, 2006
2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
Digital Signal Processors.
Proceedings of the Handbook of Networked and Embedded Control Systems, 2005
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the Computer Systems: Architectures, 2004
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
Proceedings of the Computer Systems: Architectures, 2004
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Des. Test Comput., 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the 2003 Design, 2003
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
Proceedings of the 40th Design Automation Conference, 2003
A modular simulation framework for architectural exploration of on-chip interconnection networks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the Compiler Construction, 12th International Conference, 2003
2002
Proceedings of the 2002 Joint Conference on Languages, 2002
Architecture exploration for embedded processors with LISA.
Kluwer, ISBN: 978-1-4020-7338-0, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of The Workshop on Languages, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of ASP-DAC 2001, 2001
Retargetable compiler technology for embedded systems - tools and applications.
Kluwer, ISBN: 978-0-7923-7578-4, 2001
2000
ACM Trans. Design Autom. Electr. Syst., 2000
Proceedings of the 13th International Symposium on System Synthesis, 2000
Proceedings of the 2000 Design, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000
Code optimization techniques for embedded processors - methods, algorithms, and tools.
Kluwer, ISBN: 978-0-7923-7989-8, 2000
1999
Des. Autom. Embed. Syst., 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Des. Autom. Embed. Syst., 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the ASP-DAC '98, 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Proceedings of the European Design and Test Conference, 1997
Retargetable code generation for digital signal processors.
Kluwer, ISBN: 978-0-7923-9958-2, 1997
1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995
1994
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
Proceedings of the Parallel Architectures and Compilation Techniques, 1994
Proceedings of the Proceedings EURO-DAC'94, 1994
1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993