Rainer Leupers

According to our database1, Rainer Leupers authored at least 233 papers between 1993 and 2019.

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Bibliography

2019
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs.
Embedded Systems Letters, 2019

Applying Modified Householder Transform to Kalman Filter.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Fast SystemC Processor Models with Unicorn.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

VLSI Architectures for ORVD Trellis based MIMO Detection.
Proceedings of the International Conference on Computing, Networking and Communications, 2019

Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries.
Proceedings of the 24th IEEE European Test Symposium, 2019

A heuristic for multi objective software application mappings on heterogeneous MPSoCs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018

A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping.
Proceedings of the Smart Cities, Green Technologies and Intelligent Transport Systems, 2018

A Unifying logic encryption security metric.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

VLSI implementation of channel estimation for millimeter wave beamforming training.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach.
Proceedings of the 2018 IEEE International Conference on Vehicular Electronics and Safety, 2018

Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection.
Proceedings of the 2018 International Conference on Computing, 2018

Parameterized Posit Arithmetic Hardware Generator.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
MAPS: A Software Development Environment for Embedded Multicore Applications.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Towards Parallelism Extraction for Heterogeneous Multicore Android Devices.
International Journal of Parallel Programming, 2017

DVFS-enabled power-performance trade-off in MPSoC SW application mapping.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Extraction of recursion level parallelism for embedded multicore systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment.
Proceedings of the 20th IEEE International Conference on Intelligent Transportation Systems, 2017

VLSI implementation of LS-SVM training and classification using entropy based subset-selection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition.
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Multi-grained performance estimation for MPSoC compilers: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing.
IEEE Trans. VLSI Syst., 2016

Parallel SystemC Simulation for ESL Design.
ACM Trans. Embedded Comput. Syst., 2016

Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model.
ACM Trans. Embedded Comput. Syst., 2016

MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs.
ACM Trans. Embedded Comput. Syst., 2016

A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method.
IEEE Trans. on Circuits and Systems, 2016

Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

An optimal allocation of memory buffers for complex multicore platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

Black box ESL power estimation for loosely-timed TLM models.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Concurrent memory subsystem and application optimization for ASIP design.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Automatic recognition of computational kernels for platform-dependent code optimizations.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

ORVD-Trellis based MIMO detection.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A flexible MCMC detector ASIC.
Proceedings of the International SoC Design Conference, 2016

Black box power estimation for digital signal processors using virtual platforms.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

SystemC-link: Parallel SystemC simulation using time-decoupled segments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Technology Transfer in computing systems: The TETRACOM approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP.
IEEE Trans. VLSI Syst., 2015

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Parallel SystemC simulation for ESL design using flexible time decoupling.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

ESL power estimation using virtual platforms with black box processor models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Deterministic event-based control of Virtual Platforms for MPSoC software debugging.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Parallelism extraction in embedded software for android devices.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Design and synthesis of reconfigurable control-flow structures for CGRA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A comparative investigation of device-specific mechanisms for exploiting HPC accelerators.
Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Extraction of Kahn Process Networks from While Loops in Embedded Software.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

Multi/many-core programming: where are we standing?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Parallel Density-Based Stream Clustering Using a Multi-user GPU Scheduler.
Proceedings of the Beyond Databases, Architectures and Structures, 2015

SWAT: Assertion-based debugging of concurrency issues at system level.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Unified Identification of Multiple Forms of Parallelism in Embedded Applications.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
legaSCi: Legacy SystemC Model Integration into Parallel Simulators.
ACM Trans. Embedded Comput. Syst., 2014

A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Improving ESL power models using switching activity information from timed functional models.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Pre-architectural performance estimation for ASIP design based on abstract processor models.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A heuristic for logical data buffer allocation in multicore platforms.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture.
Proceedings of the IEEE International Conference on Communications, 2014

VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Time-decoupled parallel SystemC simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Optimized buffer allocation in multicore platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Automatic detection of concurrency bugs through event ordering constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Technology transfer towards Horizon 2020.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A flexible ASIP architecture for connected components labeling in embedded vision applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Software Compilation Techniques for MPSoCs.
Proceedings of the Handbook of Signal Processing Systems, 2013

MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs.
IEEE Trans. Industrial Informatics, 2013

Efficient Implementation of Application-Aware Spinlock Control in MPSoCs.
IJERTCS, 2013

DSPACE hardware architecture for on-board real-time image/video processing in European space missions.
Proceedings of the Real-Time Image and Video Processing 2013, 2013

CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A compiler infrastructure for embedded heterogeneous MPSoCs.
Proceedings of the 2013 PPOPP International Workshop on Programming Models and Applications for Multicores and Manycores, 2013

Mapping of MIMO Receiver Algorithms onto Application-Specific Multi-Core Platforms.
Proceedings of the ISWCS 2013, 2013

Split-cost communication model for improved MPSoC application mapping.
Proceedings of the 2013 International Symposium on System on Chip, 2013

legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Creation of ESL power models for communication architectures using automatic calibration.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A New Space Digital Signal Processor Design.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

2012
Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Application-aware spinlock control using a hardware scheduler in MPSoC platforms.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

SCandal: SystemC Analysis for Nondeterminism Anomalies.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Scandal: Systemc analysis for nondeterminism anomalies.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Virtual platforms: Breaking new grounds.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Hybrid simulation for extensible processor cores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synchronization for hybrid MPSoC full-system simulation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Communication-aware mapping of KPN applications onto heterogeneous MPSoCs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Fast graph-based instruction selection for multi-output instructions.
Softw., Pract. Exper., 2011

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
IJERTCS, 2011

Checkpointing SystemC-Based Virtual Platforms.
IJERTCS, 2011

A retargetable framework for compiler/architecture co-development.
Design Autom. for Emb. Sys., 2011

Enhanced structural analysis for C code reconstruction from IR code.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

Trends in embedded software synthesis.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Automatic calibration of streaming applications for software mapping exploration.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Virtual Manycore platforms: Moving towards 100+ processor cores.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.
IEEE Trans. on Circuits and Systems, 2010

Analytical and Simulation-based Design Space Exploration of Software Defined Radios.
International Journal of Parallel Programming, 2010

Automatic Generation of Memory Interfaces for ASIPs.
IJERTCS, 2010

System level MPSoC design: a bright future for compiler technology?
Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010



Towards Network Centric Development of Embedded Systems.
Proceedings of IEEE International Conference on Communications, 2010

Cool MPSoC programming.
Proceedings of the Design, Automation and Test in Europe, 2010

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms.
Proceedings of the Design, Automation and Test in Europe, 2010

parSC: synchronous parallel systemc simulation on multi-core host architectures.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

MPSoC programming using the MAPS compiler.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Software Compilation Techniques for MPSoCs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
A SIMD optimization framework for retargetable compilers.
TACO, 2009

Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves.
IACR Cryptology ePrint Archive, 2009

A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations.
Proceedings of the Third IEEE International Conference on Secure Software Integration and Reliability Improvement, 2009

A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).
Proceedings of the Embedded Computer Systems: Architectures, 2009

Task management in MPSoCs: An ASIP approach.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Programming MPSoC platforms: Road works ahead!
Proceedings of the Design, Automation and Test in Europe, 2009

TotalProf: a fast and accurate retargetable source code profiler.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A high-level virtual platform for early MPSoC software development.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. VLSI Syst., 2008

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst., 2008

Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
JCP, 2008

SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
IJES, 2008

Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
IJES, 2008

System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Retargetable Code Optimization for Predicated Execution.
Proceedings of the Design, Automation and Test in Europe, 2008

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Multiprocessor performance estimation using hybrid simulation.
Proceedings of the 45th Design Automation Conference, 2008

MAPS: an integrated framework for MPSoC application parallelization.
Proceedings of the 45th Design Automation Conference, 2008

2007
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Increasing data-bandwidth to instruction-set extensions through register clustering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design space exploration of partially re-configurable embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A code-generator generator for multi-output instructions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

HySim: a fast simulation framework for embedded software development.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A fast and generic hybrid simulation approach using C virtual machine.
Proceedings of the 2007 International Conference on Compilers, 2007

Optimized ASIP synthesis from architecture description language models.
Kluwer, ISBN: 978-1-4020-5685-7, 2007

2006
Offset assignment using simultaneous variable coalescing.
ACM Trans. Embedded Comput. Syst., 2006

Integrated Verification Approach during ADL-Driven Processor Design.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Memory Access Micro-Profiling for ASIP Design.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

An interprocedural code optimization technique for network processors using hardware multi-threading support.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A design flow for configurable embedded processors based on optimized instruction set extension synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

ASIP design and synthesis for non linear filtering in image processing.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Automatic ADL-based operand isolation for embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

An integrated open framework for heterogeneous MPSoC design space exploration.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Retargetable code optimization with SIMD instructions.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Integrated system-level modeling of network-on-chip enabled multi-processor platforms.
Kluwer, ISBN: 978-1-4020-4825-8, 2006

2005
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
Proceedings of the 2005 Design, 2005

C Compiler Retargeting Based on Instruction Semantics Models.
Proceedings of the 2005 Design, 2005

Fine-grained application source code profiling for ASIP design.
Proceedings of the 42nd Design Automation Conference, 2005

Retargetable generation of TLM bus interfaces for MP-SoC platforms.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Digital Signal Processors.
Proceedings of the Handbook of Networked and Embedded Control Systems, 2005

2004
A universal technique for fast and flexible instruction-set architecture simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Early ISS Integration into Network-on-Chip Designs.
Proceedings of the Computer Systems: Architectures, 2004

Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
Proceedings of the Computer Systems: Architectures, 2004

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
Proceedings of the Computer Systems: Architectures, 2004

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
Proceedings of the 2004 Design, 2004

RTL Processor Synthesis for Architecture Exploration and Implementation.
Proceedings of the 2004 Design, 2004

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
Proceedings of the 2004 Design, 2004

A novel approach for flexible and consistent ADL-driven ASIP design.
Proceedings of the 41th Design Automation Conference, 2004

Compiler based exploration of DSP energy savings by SIMD operations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Instruction Scheduler Generation for Retargetable Compilation.
IEEE Design & Test of Computers, 2003

Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Improving Offset Assignment through Simultaneous Variable Coalescing.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Processor/Memory Co-Exploration on Multiple Abstraction Levels.
Proceedings of the 2003 Design, 2003

Instruction encoding synthesis for architecture exploration using hierarchical processor models.
Proceedings of the 40th Design Automation Conference, 2003

A modular simulation framework for architectural exploration of on-chip interconnection networks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms.
Proceedings of the Compiler Construction, 12th International Conference, 2003

2002
Compiler Design Issues for Embedded Processors.
IEEE Design & Test of Computers, 2002

Application specific compiler/architecture codesign: a case study.
Proceedings of the 2002 Joint Conference on Languages, 2002

A universal technique for fast and flexible instruction-set architecture simulation.
Proceedings of the 39th Design Automation Conference, 2002

Architecture exploration for embedded processors with LISA.
Kluwer, ISBN: 978-1-4020-7338-0, 2002

2001
C compiler design for a network processor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

C Compiler Design for an Industrial Network Processor.
Proceedings of The Workshop on Languages, 2001

Low-Energy DSP Code Generation Using a Genetic Algorithm.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Variable partitioning for dual memory bank DSPs.
Proceedings of the IEEE International Conference on Acoustics, 2001

Optimized address assignment for DSPs with SIMD memory accesses.
Proceedings of ASP-DAC 2001, 2001

Retargetable compiler technology for embedded systems - tools and applications.
Kluwer, ISBN: 978-0-7923-7578-4, 2001

2000
Graph-based code selection techniques for embedded processors.
ACM Trans. Design Autom. Electr. Syst., 2000

Code Generation for Embedded Processors.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Code Selection for Media Processors with SIMD Instructions.
Proceedings of the 2000 Design, 2000

Register allocation for common subexpressions in DSP data paths.
Proceedings of ASP-DAC 2000, 2000

Instruction Scheduling for Clustered VLIW DSPs.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

Code optimization techniques for embedded processors - methods, algorithms, and tools.
Kluwer, ISBN: 978-0-7923-7989-8, 2000

1999
Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths.
Design Autom. for Emb. Sys., 1999

Array Index Allocation under Register Constraints in DSP Programs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Function inlining under code size constraints for embedded processors.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors.
Proceedings of the 1999 Design, 1999

Constraint Driven Code Selection for Fixed-Point DSPs.
Proceedings of the 36th Conference on Design Automation, 1999

Generation of Interpretive and Compiled Instruction Set Simulators.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Retargetable Code Generation Based on Structural Processor Description.
Design Autom. for Emb. Sys., 1998

A Uniform Optimization Technique for Offset Assignment Problems.
Proceedings of the 11th International Symposium on System Synthesis, 1998

HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Register-Constrained Address Computation in DSP Programs.
Proceedings of the 1998 Design, 1998

Optimized Array Index Computation in DSP Programs.
Proceedings of the ASP-DAC '98, 1998

1997
Retargetable generation of code selectors from HDL processor models.
Proceedings of the European Design and Test Conference, 1997

Retargetable code generation for digital signal processors.
Kluwer, ISBN: 978-0-7923-9958-2, 1997

1996
Instruction-Set Modeling for ASIP Code Generation.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Algorithms for address assignment in DSP code generation.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Instruction selection for embedded DSPs with complex instructions.
Proceedings of the conference on European design automation, 1996

1995
Time-constrained code compaction for DSPs.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

A BDD-based frontend for retargetable compilers.
Proceedings of the 1995 European Design and Test Conference, 1995

Using compilers for heterogeneous system design.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994
Retargetable assembly code generation by bootstrapping.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Microcode Generation for Flexible Parallel Target Architectures.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

Instruction set extraction from programmable structures.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
Resistance Extraction using a Routing Algorithm.
Proceedings of the 30th Design Automation Conference. Dallas, 1993


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