Luis Gabriel Murillo

According to our database1, Luis Gabriel Murillo authored at least 16 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
DVFS-enabled power-performance trade-off in MPSoC SW application mapping.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016
Parallel SystemC Simulation for ESL Design.
ACM Trans. Embedded Comput. Syst., 2016

MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs.
ACM Trans. Embedded Comput. Syst., 2016

Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
Journal of Systems Architecture - Embedded Systems Design, 2016

Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Deterministic event-based control of Virtual Platforms for MPSoC software debugging.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

SWAT: Assertion-based debugging of concurrency issues at system level.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Pre-architectural performance estimation for ASIP design based on abstract processor models.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Automatic detection of concurrency bugs through event ordering constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Hybrid simulation for extensible processor cores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synchronization for hybrid MPSoC full-system simulation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2009
Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulators.
Proceedings of the Forum on specification and Design Languages, 2009

2008
Model-based Design Space Exploration for RTES with SysML and MARTE.
Proceedings of the Forum on specification and Design Languages, 2008


  Loading...