Juan Fernando Eusse
According to our database1, Juan Fernando Eusse authored at least 18 papers between 2009 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA.
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs.
Embedded Systems Letters, 2019
MAPS: A Software Development Environment for Embedded Multicore Applications.
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Towards Parallelism Extraction for Heterogeneous Multicore Android Devices.
International Journal of Parallel Programming, 2017
Extraction of recursion level parallelism for embedded multicore systems.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Concurrent memory subsystem and application optimization for ASIP design.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design.
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Parallelism extraction in embedded software for android devices.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Extraction of Kahn Process Networks from While Loops in Embedded Software.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
Pre-architectural performance estimation for ASIP design based on abstract processor models.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
A flexible ASIP architecture for connected components labeling in embedded vision applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A Protein Sequence Analysis Hardware Accelerator Based on Divergences.
Int. J. Reconfig. Comp., 2012
Hybrid simulation for extensible processor cores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Synchronization for hybrid MPSoC full-system simulation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
A HMMER hardware accelerator using divergences.
Proceedings of the Design, Automation and Test in Europe, 2010
BRICK: a multi-context expression grained reconfigurable architecture.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Signal Processing Domain Application Mapping on the Brick Reconfigurable Array.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009