Giuseppe Lettieri

Orcid: 0000-0003-1005-7441

According to our database1, Giuseppe Lettieri authored at least 43 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
Improving Live Migration Efficiency in QEMU: A Paravirtualized Approach.
Proceedings of the High Performance Computing, 2023

SmartNIC-Accelerated Stream Processing Analytics.
Proceedings of the IEEE Conference on Network Function Virtualization and Software Defined Networks, 2023

An Analysis System to Test Security of Software on Continuous Integration-Continuous Delivery Pipeline.
Proceedings of the IEEE European Symposium on Security and Privacy, 2023

2022
Programming socket-independent network functions with nethuns.
Comput. Commun. Rev., 2022

eBPF-based Extensible Paravirtualization.
Proceedings of the High Performance Computing. ISC High Performance 2022 International Workshops - Hamburg, Germany, May 29, 2022

Mind the cost of telemetry data analysis.
Proceedings of the SIGCOMM '22 Poster and Demo Sessions, 2022

2021
Data Stream Processing for Packet-Level Analytics.
Sensors, 2021

Towards Scalable and Expressive Stream Packet Processing.
Proceedings of the IEEE Global Communications Conference, 2021

2019
Cache-aware design of general-purpose Single-Producer-Single-Consumer queues.
Softw. Pract. Exp., 2019

BPFHV: Adaptive Network Paravirtualization for Continuous Cloud Provider Evolution.
Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018
PSPAT: Software packet scheduling at hardware speed.
Comput. Commun., 2018

A Study of I/O Performance of Virtual Machines.
Comput. J., 2018

PASTE: A Network Programming Interface for Non-Volatile Main Memory.
Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation, 2018

2017
A Survey of Fast Packet I/O Technologies for Network Function Virtualization.
Proceedings of the High Performance Computing, 2017

HyperNF: building a high performance, high utilization and fair NFV platform.
Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, 2017

2016
Heuristic search for equivalence checking.
Softw. Syst. Model., 2016

Very high speed link emulation with TLEM.
Proceedings of the IEEE International Symposium on Local and Metropolitan Area Networks, 2016

Flexible virtual machine networking using netmap passthrough.
Proceedings of the IEEE International Symposium on Local and Metropolitan Area Networks, 2016

A Study of Speed Mismatches Between Communicating Virtual Machines.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

2015
mSwitch: a highly-scalable, modular software switch.
Proceedings of the 1st ACM SIGCOMM Symposium on Software Defined Networking Research, 2015

k-Bisimulation: A Bisimulation for Measuring the Dissimilarity Between Processes.
Proceedings of the Formal Aspects of Component Software - 12th International Conference, 2015

Virtual Device Passthrough for High Speed VM Networking.
Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, 2015

2014
GreASE: A Tool for Efficient "Nonequivalence" Checking.
ACM Trans. Softw. Eng. Methodol., 2014

2013
Speeding up packet I/O in virtual machines.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2013

2012
An Abstract Interpretation framework for genotype elimination algorithms.
Theor. Comput. Sci., 2012

Efficient Genotype Elimination via Adaptive Allele Consolidation.
IEEE ACM Trans. Comput. Biol. Bioinform., 2012

VALE, a switched ethernet for virtual machines.
Proceedings of the Conference on emerging Networking Experiments and Technologies, 2012

2010
Using abstract interpretation to add type checking for interfaces in Java bytecode verification.
Theor. Comput. Sci., 2010

Partial model checking via abstract interpretation.
Inf. Process. Lett., 2010

Celer: an Efficient Program for Genotype Elimination
Proceedings of the Proceedings First Workshop on Applications of Membrane computing, 2010

2008
Decomposing bytecode verification by abstract interpretation.
ACM Trans. Program. Lang. Syst., 2008

2006
Using postdomination to reduce space requirements of data flow analysis.
Inf. Process. Lett., 2006

Caching and prefetching algorithms for programs with looping reference patterns.
Comput. J., 2006

Using Control Dependencies for Space-Aware Bytecode Verification.
Comput. J., 2006

2005
A Space-Aware Bytecode Verifier for Java Cards.
Proceedings of the First Workshop on Bytecode Semantics, 2005

2004
Checking secure information flow in Java bytecode by code transformation and standard bytecode verification.
Softw. Pract. Exp., 2004

Concrete and Abstract Semantics to Check Secure Information Flow in Concurrent Programs.
Fundam. Informaticae, 2004

2003
Checking security properties by model checking.
Softw. Test. Verification Reliab., 2003

2002
An abstract semantics tool for secure information flow of stack-based assembly programs.
Microprocess. Microsystems, 2002

Using Standard Verifier to Check Secure Information Flow in Java Bytecode.
Proceedings of the 26th International Computer Software and Applications Conference (COMPSAC 2002), 2002

2000
An Overview of Ulisse, a Distributed Single Address Space System.
Proceedings of the Persistent Object Systems, 9th International Workshop, 2000

1999
Implementing a Distributed Single Address Space in the Presence of Failures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Recoverable-Persistence in a Distributed Single Address Space.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999


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