Cinzia Bernardeschi

According to our database1, Cinzia Bernardeschi authored at least 69 papers between 1992 and 2018.

Collaborative distances:



In proceedings 
PhD thesis 





Verifying data secure flow in AUTOSAR models.
J. Computer Virology and Hacking Techniques, 2018

A PVS-Simulink Integrated Environment for Model-Based Analysis of Cyber-Physical Systems.
IEEE Trans. Software Eng., 2018

OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.
IEEE Trans. Emerging Topics Comput., 2018

A Flexible Framework for FMI-Based Co-Simulation of Human-Centred Cyber-Physical Systems.
Proceedings of the Software Technologies: Applications and Foundations, 2018

Demo: Co-simulation of UAVs with INTO-CPS and PVSio-web.
Proceedings of the Software Technologies: Applications and Foundations, 2018

Towards Stochastic FMI Co-Simulations: Implementation of an FMU for a Stochastic Activity Networks Simulator.
Proceedings of the Software Technologies: Applications and Foundations, 2018

PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

Data Leakage in Java Applets with Exception Mechanism.
Proceedings of the Second Italian Conference on Cyber Security, Milan, Italy, February 6th - to, 2018

Co-simulation of Semi-autonomous Systems: The Line Follower Robot Case Study.
Proceedings of the Software Engineering and Formal Methods, 2017

Modeling and generation of secure component communications in AUTOSAR.
Proceedings of the Symposium on Applied Computing, 2017

Verifying Data Secure Flow in AUTOSAR Models by Static Analysis.
Proceedings of the 3rd International Conference on Information Systems Security and Privacy, 2017

Towards a Formalization of System Requirements for an Integrated Clinical Environment.
EAI Endorsed Trans. Self-Adaptive Systems, 2016

Verifying safety properties of a nonlinear control by interactive theorem proving with the Prototype Verification System.
Inf. Process. Lett., 2016

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.
Integration, 2016

Extending a User Interface Prototyping Tool with Automatic MISRA C Code Generation.
Proceedings of the Third Workshop on Formal Integrated Development Environment, 2016

Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation.
Ad Hoc & Sensor Wireless Networks, 2016

Using Smartwatch Sensors to Support the Acquisition of Sleep Quality Data for Supervised Machine Learning.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Detecting Elderly Behavior Shift via Smart Devices and Stigmergic Receptive Fields.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Using AUTOSAR High-Level Specifications for the Synthesis of Security Components in Automotive Systems.
Proceedings of the Modelling and Simulation for Autonomous Systems, 2016

Modeling communication network requirements for an integrated clinical environment in the Prototype Verification System.
Proceedings of the IEEE Symposium on Computers and Communication, 2016

SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies.
J. Comput. Sci. Technol., 2015

Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries.
IEEE Trans. Industrial Informatics, 2014

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Combining PVSio with Stateflow.
Proceedings of the NASA Formal Methods - 6th International Symposium, NFM 2014, Houston, TX, USA, April 29, 2014

An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs.
Journal of Systems Architecture - Embedded Systems Design, 2013

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Formal approaches to SEU testing in FPGAs.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

JCSI: A tool for checking secure information flow in Java Card applications.
Journal of Systems and Software, 2012

SEU-X: A SEu un-excitability prover for SRAM-FPGAs.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Failure Probability and Fault Observability of SRAM-FPGA Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Failure probability of SRAM-FPGA systems with Stochastic Activity Networks.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Analysis of Wireless Sensor Network Protocols in Dynamic Scenarios.
Proceedings of the Stabilization, 2009

Decomposing bytecode verification by abstract interpretation.
ACM Trans. Program. Lang. Syst., 2008

Early Prototyping of Wireless Sensor Network Algorithms in PVS.
Proceedings of the Computer Safety, 2008

Using postdomination to reduce space requirements of data flow analysis.
Inf. Process. Lett., 2006

Using Control Dependencies for Space-Aware Bytecode Verification.
Comput. J., 2006

A Space-Aware Bytecode Verifier for Java Cards.
Electr. Notes Theor. Comput. Sci., 2005

FACT: A Tool for Code Generation from Communicating Automata.
Proceedings of the IASTED International Conference on Software Engineering, 2005

Checking secure information flow in Java bytecode by code transformation and standard bytecode verification.
Softw., Pract. Exper., 2004

Concrete and Abstract Semantics to Check Secure Information Flow in Concurrent Programs.
Fundam. Inform., 2004

Analyzing Information Flow Properties in Assembly Code by Abstract Interpretation.
Comput. J., 2004

Java bytecode verification with dynamic structures.
Proceedings of the IASTED Conference on Software Engineering and Applications, 2004

Enforcement of applet boundaries in Java card systems.
Proceedings of the IASTED Conference on Software Engineering and Applications, 2004

Efficient Bytecode Verification Using Immediate Postdominators in Control Flow Graphs: Extended Abstract.
Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003

Model checking fault tolerant systems.
Softw. Test., Verif. Reliab., 2002

An abstract semantics tool for secure information flow of stack-based assembly programs.
Microprocessors and Microsystems, 2002

Abstract interpretation of operational semantics for secure information flow.
Inf. Process. Lett., 2002

Combining Abstract Interpretation and Model Checking for Analysing Security Properties of Java Bytecode.
Proceedings of the Verification, 2002

Fixing the Java bytecode verifier by a suitable type domain.
Proceedings of the 14th international conference on Software engineering and knowledge engineering, 2002

Checking security of Java bytecode by abstract interpretation.
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

Using Standard Verifier to Check Secure Information Flow in Java Bytecode.
Proceedings of the 26th International Computer Software and Applications Conference (COMPSAC 2002), 2002

Formal validation of fault-tolerance mechanisms inside GUARDS.
Rel. Eng. & Sys. Safety, 2001

An approach to system design based on P/T net simulation.
Information & Software Technology, 2001

Formally Verifying Fault Tolerant System Designs.
Comput. J., 2000

Formal Validation of the GUARDS Inter-Consistency Mechanism.
Proceedings of the Computer Safety, 1999

A Formal Verification Environment for Railway Signaling System Design.
Formal Methods in System Design, 1998

Temporal analysis of data flow control systems.
Automatica, 1998

Validating the Design of Dependable Systems.
Proceedings of the 1st International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC '98), 1998

An industrial application for the JACK environment.
Journal of Systems and Software, 1997

Proving Safety Properties for Embedded Control Systems.
Proceedings of the Dependable Computing, 1996

Using Process Algebras for the Semantic Analysis of Data Flow Networks.
IEICE Transactions, 1995

A Petri Nets Semantics for Data Flow Networks.
Acta Inf., 1995

Application of Correctness Preserving Transformations for Deriving Architectural Descriptions of Interactive Systems from User Interface Specifications.
Proceedings of the SEKE'95, 1995

Formal Reasoning on Fault Coverage of Fault Tolerant Techniques: A Case Study.
Proceedings of the Dependable Computing, 1994

From Data Flow Networks to Process Algebras.
Proceedings of the PARLE '93, 1993

The Design of Distributed, Dependable Real-Time Systems Using a Functional Paradigm.
Proceedings of the Real Time Computing, 1992