Gordon B. Steven

According to our database, Gordon B. Steven authored at least 24 papers between 1988 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2003

Two-level branch prediction using neural networks.

Colin Egan, Gordon B. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan

J. Syst. Archit., 2003

2002

Cached Two-Level Adaptive Branch Predictors with Multiple Stages.

Colin Egan, Gordon B. Steven, Lucian N. Vintan

Proceedings of the Trends in Network and Pervasive Computing, 2002

2001

Adding static data dependence collapsing to a high-performance instruction scheduler.

Fleur L. Steven, Colin Egan, Richard D. Potter, Gordon B. Steven

J. Syst. Archit., 2001

Dynamic Branch Prediction Using Neural Networks.

Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Applying Caching to Two-Level Adaptive Branch Prediction.

Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Static Scheduling for Out-of-order Instruction Issue Processors.

Daniel Tate, Gordon B. Steven, Fleur L. Steven

Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999

The impact of cache organisation on the instruction issue rate of a superscalar processor.

Lucian N. Vintan, Cristian Armat, Gordon B. Steven

Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

1998

The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture.

Daniel Tate, Gordon B. Steven, Paul A. Findlay

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

A superscalar architecture to exploit instruction level parallelism.

Gordon B. Steven, Bruce Christianson, Roger Collins, Richard D. Potter, Fleur L. Steven

Microprocess. Microsystems, 1997

1996

Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture.

Richard D. Potter, Gordon B. Steven

Proceedings of the Euro-Par '96 Parallel Processing, 1996

Instruction Scheduling for a Superscalar Architecture.

Roger Collins, Gordon B. Steven

Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995

Hades-towards the design of an asynchronous superscalar processor.

C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994

An explicitly declared delayed-branch mechanism for a superscalar architecture.

Roger Collins, Gordon B. Steven

Microprocess. Microprogramming, 1994

Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler.

Rod Adams, Sue M. Gray, Gordon B. Steven

Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

1993

Static instruction scheduling for the HARP multiple-instruction-issue architecture.

Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven

Microprocess. Microsystems, 1993

ALU design and processor branch architecture.

Gordon B. Steven, Fleur L. Steven

Microprocess. Microprogramming, 1993

Addressing mechanisms for VLIW and superscalar processors.

Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale

Microprocess. Microprogramming, 1993

1991

A parallel pipelined processor with conditional instruction execution.

Rod Adams, Gordon B. Steven

SIGARCH Comput. Archit. News, 1991

1990

Address and data register separation on the M68000 family.

Fleur L. Williams, Gordon B. Steven

SIGARCH Comput. Archit. News, 1990

How useful are complex instructions? A case study using the M68000.

Fleur L. Williams, Gordon B. Steven

Microprocessing and Microprogramming, 1990

Utilising low level parallelism in general purpose code: the HARP project.

R. G. Adams, Sue M. Gray, Gordon B. Steven

Microprocessing and Microprogramming, 1990

1989

HARP: A parallel pipelined RISC processor.

Gordon B. Steven, Sue M. Gray, R. G. Adams

Microprocess. Microsystems, 1989

1988

A novel effective address calculation mechanism for RISC microprocessors.

Gordon B. Steven

SIGARCH Comput. Archit. News, 1988

General addressing mechanisms for microprocessors.

Gordon B. Steven, Fleur L. Williams

Microprocess. Microsystems, 1988