Gordon B. Steven

According to our database1, Gordon B. Steven authored at least 19 papers between 1988 and 2002.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2002
Cached Two-Level Adaptive Branch Predictors with Multiple Stages.
Proceedings of the Trends in Network and Pervasive Computing, 2002

2001
Adding static data dependence collapsing to a high-performance instruction scheduler.
Journal of Systems Architecture, 2001

Dynamic Branch Prediction Using Neural Networks.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Applying Caching to Two-Level Adaptive Branch Prediction.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000
Static Scheduling for Out-of-order Instruction Issue Processors.
Proceedings of the 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January, 2000

1999
The impact of cache organisation on the instruction issue rate of a superscalar processor.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

1998
The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
A superscalar architecture to exploit instruction level parallelism.
Microprocess. Microsystems, 1997

1996
Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Instruction Scheduling for a Superscalar Architecture.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995
Hades-towards the design of an asynchronous superscalar processor.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1994
An explicitly declared delayed-branch mechanism for a superscalar architecture.
Microprocessing and Microprogramming, 1994

Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

1993
Static instruction scheduling for the HARP multiple-instruction-issue architecture.
Microprocess. Microsystems, 1993

ALU design and processor branch architecture.
Microprocessing and Microprogramming, 1993

Addressing mechanisms for VLIW and superscalar processors.
Microprocessing and Microprogramming, 1993

1991
A parallel pipelined processor with conditional instruction execution.
SIGARCH Computer Architecture News, 1991

1989
HARP: A parallel pipelined RISC processor.
Microprocess. Microsystems, 1989

1988
General addressing mechanisms for microprocessors.
Microprocess. Microsystems, 1988


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