Gregor Sievers

According to our database, Gregor Sievers authored at least 10 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories.

Johannes Ax, Gregor Sievers, Julian Daberkow, Martin Flasskamp, Marten Vohrmann, Thorsten Jungeblut, Wayne Kelly, Mario Porrmann, Ulrich Rückert

IEEE Trans. Parallel Distributed Syst., 2018

2016

Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen.

Gregor Sievers

PhD thesis, 2016

Performance estimation of streaming applications for hierarchical MPSoCs.

Martin Flasskamp, Gregor Sievers, Johannes Ax, Christian Klarhorst, Thorsten Jungeblut, Wayne Kelly, Michael Thies, Mario Porrmann

Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

2015

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs.

Johannes Ax, Gregor Sievers, Martin Flasskamp, Wayne Kelly, Thorsten Jungeblut, Mario Porrmann

Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.

Gregor Sievers, Julian Daberkow, Johannes Ax, Martin Flasskamp, Wayne Kelly, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI.

Gregor Sievers, Johannes Ax, Nils Kucza, Martin Flasskamp, Thorsten Jungeblut, Wayne Kelly, Mario Porrmann, Ulrich Rückert

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC.

Wayne Kelly, Martin Flasskamp, Gregor Sievers, Johannes Ax, Jianing Chen, Christian Klarhorst, Christoph Ragg, Thorsten Jungeblut, Andrew Sorensen

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture.

Boris Hübener, Gregor Sievers, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.

Gregor Sievers, Peter Christ, Julian Einhaus, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2010

Design Space Exploration for Memory Subsystems of VLIW Architectures.

Thorsten Jungeblut, Gregor Sievers, Mario Porrmann, Ulrich Rückert

Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010