Paul Racunas

According to our database, Paul Racunas authored at least 11 papers between 1997 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Characterizing and Mitigating Soft Errors in GPU DRAM.

Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler

IEEE Micro, 2022

2020

Estimating Silent Data Corruption Rates Using a Two-Level Model.

Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler

CoRR, 2020

On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors.

Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas

Proceedings of the IEEE International Test Conference, 2020

2019

Resiliency of automotive object detection networks on GPU architectures.

Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang

Proceedings of the IEEE International Test Conference, 2019

2018

Low Overhead Tag Error Mitigation for GPU Architectures.

Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani

Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

2015

A fast and accurate analytical technique to compute the AVF of sequential bits in a processor.

Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer

Proceedings of the 48th International Symposium on Microarchitecture, 2015

2008

Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal.

Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee

IEEE Comput. Archit. Lett., 2008

2007

Perturbation-based Fault Screening.

Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2005

Computing Architectural Vulnerability Factors for Address-Based Structures.

Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2003

Partitioned first-level cache design for clustered microarchitectures.

Paul Racunas, Yale N. Patt

Proceedings of the 17th Annual International Conference on Supercomputing, 2003

1997

Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.

Jared Stark, Paul Racunas, Yale N. Patt

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997