Guangyi Lu

According to our database, Guangyi Lu authored at least 16 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique.

Jiahao Wei, Weiqi Chen, Yajie Gong, Qi Wu, Guangyi Lu, Wei Gao, Lihui Wang, Mei Li, Haiming Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

2020

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics.

Yize Wang, Guangyi Lu, Yuan Wang

IEEE Access, 2020

2018

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.

Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness.

Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang

IEICE Trans. Electron., 2017

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress.

Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang

IEICE Electron. Express, 2017

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.

Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process.

Guangyi Lu, Yuan Wang, Xing Zhang

IEICE Trans. Electron., 2016

A novel SPICE circuit model of electrostatic discharge (ESD) generator.

Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang

IEICE Electron. Express, 2016

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process.

Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang

Sci. China Inf. Sci., 2016

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.

Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang

Sci. China Inf. Sci., 2016

A compact SCR model using advanced BJT models and standard SPICE elements.

Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang

Sci. China Inf. Sci., 2016

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications.

Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling.

Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang

Sci. China Inf. Sci., 2015

Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection.

Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network.

Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits.

Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang

Proceedings of the IEEE 10th International Conference on ASIC, 2013