A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.

[BibT_eX]

[DOI]

Jiahao Song

Xiyuan Tang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

An Efficient Spiking Neural Network Accelerator with Sparse Weight.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Full-Neuron Memory Model Designed for Neuromorphic Systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Mapping Model of SNNs to Neuromorphic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Boosting Dense Long-Tailed Object Detection from Data-Centric View.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ACCV 2022, 2022

2021

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization.

[BibT_eX]

[DOI]

Qingyu Guo

Yuan Wang

Xiaoxin Cui

CoRR, 2021

Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach.

[BibT_eX]

[DOI]

Yuan Wang

Sebin Gracy

Hideaki Ishii

Karl Henrik Johansson

CoRR, 2021

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics.

[BibT_eX]

[DOI]

Yize Wang

Guangyi Lu

Yuan Wang

IEEE Access, 2020

Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Parallel Bitstream Generator for Stochastic Computing.

[BibT_eX]

[DOI]

CoRR, 2019

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2019

Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Survey of Computation-Driven Data Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2019

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2018

A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2017

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Compact digital-controlled neuromorphic circuit with low power consumption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A reliable true random number generator based on novel chaotic ring oscillator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A novel equivalent circuit model of the surge wave generator.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2016

A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2016

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis.

[BibT_eX]

[DOI]

Wenyi Tang

Song Jia

Yuan Wang

IEICE Trans. Electron., 2016

Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process.

[BibT_eX]

[DOI]

Guangyi Lu

Yuan Wang

Xing Zhang

IEICE Trans. Electron., 2016

A novel SPICE circuit model of electrostatic discharge (ESD) generator.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

A compact SCR model using advanced BJT models and standard SPICE elements.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2015

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2015

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A reference-less all-digital burst-mode CDR with embedded TDC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low power and high speed CAM design using pulsed voltage for search-line.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier.

[BibT_eX]

[DOI]

Jiyu Chen

Song Jia

Yuan Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2014

2013

Improved CRC Calculation Strategies for 64-bit Serial RapidIO.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

Data Convertors Design for Optimization of the DDPL Family.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

A current mode sense amplifier with self-compensation circuit for SRAM application.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel dynamic element match technique in current-steering DAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF).

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2012

2011

Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2011

A novel multi-finger layout strategy for GGnMOS ESD protection device.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Low swing drivers based on charge redistribution.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2010

2007

Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Yuan Wang

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