Guei-Yuan Lueh

According to our database1, Guei-Yuan Lueh authored at least 26 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
C-for-Metal: High Performance Simd Programming on Intel GPUs.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2019
SIMD-node Transformations for Non-blocking Data Structures.
Proceedings of the Parallel Processing and Applied Mathematics, 2019

A Lock-Free Skiplist for Integrated Graphics Processing Units.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

IGC: The Open Source Intel Graphics Compiler.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

2018
Register allocation for Intel processor graphics.
Proceedings of the 2018 International Symposium on Code Generation and Optimization, 2018

2011
Bothnia: a dual-personality extension to the Intel integrated graphics driver.
ACM SIGOPS Oper. Syst. Rev., 2011

2007
The XTREM power and performance simulator for the Intel XScale core: Design and experiences.
ACM Trans. Embed. Comput. Syst., 2007

EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

2006
Data and Computation Transformations for Brook Streaming Applications on Multiprocessors.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.
Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006

2005
Parallel Processing of A Raytracer for GPU vs. for CPU.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A Code Generation Algorithm for Affine Partitioning Framework.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

2004
XTREM: a power simulator for the Intel XScale® core.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Code sharing among states for stack-caching interpreter.
Proceedings of the 2004 Workshop on Interpreters, Virtual Machines and Emulators, 2004

2003
Inter-procedural stacked register allocation for itanium® like architecture.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

2002
Recompilation for debugging support in a JIT-compiler.
Proceedings of the 2002 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis For Software Tools and Engineering, 2002

Just-In-Time Java? Compilation for the Itanium® Processor.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2000
Fusion-based register allocation.
ACM Trans. Program. Lang. Syst., 2000

Practicing JUDO: Java under dynamic optimizations.
Proceedings of the 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2000

1999
Support for Garbage Collection at Every Instruction in a Java Compiler.
Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1999

1998
Fast, Effective Code Generation in a Just-In-Time Java Compiler.
Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998

1997
Call-Cost Directed Register Allocation.
Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), 1997

1996
Code Reuse in an Optimizing Compiler.
Proceedings of the 1996 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 1996

Global Register Allocation Based on Graph Fusion.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

1993
Modeling Instruction-Level Parallelism for Software Pipelining.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993


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