Hong Wang

Affiliations:
  • Intel Santa Clara, California


According to our database1, Hong Wang authored at least 42 papers between 1991 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
MARS: Memory Aware Reordered Source.
CoRR, 2018

Tackling memory access latency through DRAM row management.
Proceedings of the International Symposium on Memory Systems, 2018

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2011
Bothnia: a dual-personality extension to the Intel integrated graphics driver.
ACM SIGOPS Oper. Syst. Rev., 2011

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture.
Proceedings of the 8th Conference on Computing Frontiers, 2011

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Intel nehalem processor core made FPGA synthesizable.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

BLoG: post-silicon bug localization in processors using bug localization graphs.
Proceedings of the 47th Design Automation Conference, 2010

2009
Criticality-based optimizations for efficient load processing.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Intel® atom<sup>TM</sup> processor core made FPGA-synthesizable.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.
IEEE Trans. Parallel Distributed Syst., 2008

CPR: Composable performance regression for scalable multiprocessor models.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Processor Performance Modeling using Symbolic Simulation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Merge: a programming model for heterogeneous multi-core systems.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Sequencer virtualization.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006
Multiple Instruction Stream Processor.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005
A Dependency Chain Clustered Microarchitecture.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Helper Threads via Virtual Multithreading.
IEEE Micro, 2004

Control Flow Optimization Via Dynamic Reconvergence Prediction.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Best of Both Latency and Throughput.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Hardware Support for Prescient Instruction Prefetch.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Helper threads via virtual multithreading on an experimental itanium<sup>®</sup> 2 processor-based platform.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
A framework for modeling and optimization of prescient instruction prefetch.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations.
Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

2002
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.
Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001
Dynamic speculative precomputation.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Speculative precomputation: long-range prefetching of delinquent loads.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Register Renaming and Scheduling for Dynamic Execution of Predicated Code.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Redundant Arithmetic Optimizations (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1997
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags.
IEEE Trans. Computers, 1997

1995
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993
A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 1993

1992
On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers.
Proceedings of the 1992 International Conference on Parallel Processing, 1992

1991
Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1991


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