Bulusu Anand
Orcid: 0000-0002-3986-3730
According to our database1,
Bulusu Anand
authored at least 58 papers
between 2011 and 2023.
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Bibliography
2023
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations.
Microelectron. J., December, 2023
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023
Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm.
Proceedings of the International Conference on Microelectronics, 2021
2020
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals.
IEEE Trans. Circuits Syst., 2020
2019
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.
IEEE Trans. Very Large Scale Integr. Syst., 2019
High performance energy efficient radiation hardened latch for low voltage applications.
Integr., 2019
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.
Microelectron. J., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis.
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Efficient static D-latch standard cell characterization using a novel setup time model.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design.
Microelectron. Reliab., 2013
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices.
Microelectron. Reliab., 2013
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field.
Microelectron. J., 2013
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues.
Proceedings of the International Symposium on Electronic System Design, 2012
2011
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Efficient nanoscale VLSI standard cell library characterization using a novel delay model.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011