Arvind K. Sharma

Orcid: 0000-0002-9250-9642

According to our database1, Arvind K. Sharma authored at least 42 papers between 2006 and 2024.

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Bibliography

2024
Reinforcing the Connection between Analog Design and EDA (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.
ACM Trans. Design Autom. Electr. Syst., September, 2023

GNN-Based Hierarchical Annotation for Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Addressing image and Poisson noise deconvolution problem using deep learning approaches.
Comput. Intell., August, 2023

Performance-driven Wire Sizing for Analog Integrated Circuits.
ACM Trans. Design Autom. Electr. Syst., March, 2023

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Automation Monitoring With Sensors For Detecting Covid Using Backpropagation Algorithm.
KSII Trans. Internet Inf. Syst., 2021

ALIGN: A System for Automating Analog Layout.
IEEE Des. Test, 2021

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Machine Learning Techniques in Analog Layout Automation.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analog Layout Generation using Optimized Primitives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Learning from Experience: Applying ML to Analog Circuit Design.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A Customized Graph Neural Network Model for Guiding Analog IC Placement.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An energy-efficient variation aware self-correcting latch.
Microelectron. J., 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

2016
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.
Microelectron. J., 2016

An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis.
Proceedings of the 13th International Conference on Synthesis, 2016

A novel energy-efficient self-correcting methodology employing INWE.
Proceedings of the 13th International Conference on Synthesis, 2016

2015
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Timing model for two stage buffer and its application in ECSM characterization.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Efficient static D-latch standard cell characterization using a novel setup time model.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2009
Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator.
Proceedings of the First International Conference on Computational Intelligence, 2009

2006
A 2.8-W Q-Band High-Efficiency Power Amplifier.
IEEE J. Solid State Circuits, 2006


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