Arvind K. Sharma

According to our database, Arvind K. Sharma authored at least 42 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Reinforcing the Connection between Analog Design and EDA (Invited Paper).

Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.

Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., September, 2023

GNN-Based Hierarchical Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs.

Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Addressing image and Poisson noise deconvolution problem using deep learning approaches.

Mohammad Haider Syed, Kamal Upreti, Mohammad Shahnawaz Nasir, Mohammad Shabbir Alam, Arvind Kumar Sharma

Comput. Intell., August, 2023

Performance-driven Wire Sizing for Analog Integrated Circuits.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

ACM Trans. Design Autom. Electr. Syst., March, 2023

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.

Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 19th International Conference on Synthesis, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.

Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells.

Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.

Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.

Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.

Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Automation Monitoring With Sensors For Detecting Covid Using Backpropagation Algorithm.

Pravin Kshirsagar, Hariprasath Manoharan, Vineet Tirth, Mohd Naved, Ahmad Tasnim Siddiqui, Arvind K. Sharma

KSII Trans. Internet Inf. Syst., 2021

ALIGN: A System for Automating Analog Layout.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

IEEE Des. Test, 2021

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.

Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Machine Learning Techniques in Analog Layout Automation.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.

Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analog Layout Generation using Optimized Primitives.

Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Learning from Experience: Applying ML to Analog Circuit Design.

Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A Customized Graph Neural Network Model for Guiding Analog IC Placement.

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches.

Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu

IEEE Trans. Very Large Scale Integr. Syst., 2019

An energy-efficient variation aware self-correcting latch.

Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu

Microelectron. J., 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.

Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective.

Arvind Kumar Sharma, Naushad Alam, Anand Bulusu

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

2016

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.

Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand

Microelectron. J., 2016

An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis.

Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand

Proceedings of the 13th International Conference on Synthesis, 2016

A novel energy-efficient self-correcting methodology employing INWE.

Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu

Proceedings of the 13th International Conference on Synthesis, 2016

2015

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies.

Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Timing model for two stage buffer and its application in ECSM characterization.

Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Efficient static D-latch standard cell characterization using a novel setup time model.

Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect.

Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2009

Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator.

Amol Vasudeva, Arvind Kumar Sharma, Ashish Kumar

Proceedings of the First International Conference on Computational Intelligence, 2009

2006

A 2.8-W Q-Band High-Efficiency Power Amplifier.

Michael V. Aust, Arvind K. Sharma, Owen Fordham, Ronald Grundbacher, Richard To, Roger S. Tsai, Richard Lai

IEEE J. Solid State Circuits, 2006