Haidar M. Harmanani

Orcid: 0000-0001-5416-4383

According to our database1, Haidar M. Harmanani authored at least 39 papers between 1991 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
AraSpot: Arabic Spoken Command Spotting.
ACM Trans. Asian Low Resour. Lang. Inf. Process., July, 2024

Speech Bandwidth Expansion Via High Fidelity Generative Adversarial Networks.
CoRR, 2024

2022
Joint theme and event based rating model for identifying relevant influencers on Twitter: COVID-19 case study.
Online Soc. Networks Media, 2022

2021
A Novel Federated Fog Architecture Embedding Intelligent Formation.
IEEE Netw., 2021

ABET Accreditation: A Way Forward for PDC Education.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

A Strength Pareto Evolutionary Algorithm for Solving the Capacitated Vehicle Routing Problem with Time Windows.
Proceedings of the 13th International Joint Conference on Computational Intelligence, 2021

2020
Critical Impact of Social Networks Infodemic on Defeating Coronavirus COVID-19 Pandemic: Twitter-Based Study and Research Directions.
IEEE Trans. Netw. Serv. Manag., 2020

Cloud federation formation using genetic and evolutionary game theoretical models.
Future Gener. Comput. Syst., 2020

2018
A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules.
Int. J. Comput. Intell. Appl., 2018

2016
An enhanced light-load efficiency step down regulator with fine step frequency scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A Parallel GPU Implementation of the Timber Wolf Placement Algorithm.
Proceedings of the 12th International Conference on Information Technology, 2015

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components.
Proceedings of the 2015 IEEE International Conference on Information Reuse and Integration, 2015

2014
Efficient shaped quantizer dithering implementation for sigma delta modulators.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012
An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
Heuristic approaches for optimizing the performance of rule-based classifiers.
Proceedings of the IEEE International Conference on Information Reuse and Integration, 2011

An optimal formulation for test scheduling network-on-chip using multiple clock rates.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

A Simulated Annealing Algorithm for the Capacitated Vehicle Routing Problem.
Proceedings of the ISCA 26th International Conference on Computers and Their Applications, 2011

2010
Predicting stability of classes in an object-oriented system.
J. Comput. Methods Sci. Eng., 2010

A method for efficient NoC test scheduling using deterministic routing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Estimating test cost during data path and controller synthesis with low power overhead.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2009
A hybrid heuristic approach to optimize rule-based software quality estimation models.
Inf. Softw. Technol., 2009

A parallel genetic algorithm for the open-shop scheduling problem using deterministic and random moves.
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009

2006
Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm.
J. Circuits Syst. Comput., 2006

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints.
Int. J. Comput. Intell. Appl., 2006

A Rule-Based Extensible Stemmer for Information Retrieval with Application to Arabic.
Int. Arab J. Inf. Technol., 2006

2005
An Evolutionary Algorithm for the Allocation Problem in High-level Synthesis.
J. Circuits Syst. Comput., 2005

A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
A Parallel Genetic Algorithm For The Geometrically Constrained Site Layout Problem With Unequal-Size Facilities.
Int. J. Comput. Intell. Appl., 2004

2003
A neural networks algorithm for data path synthesis.
Comput. Electr. Eng., 2003

2002
A Parallel Neural Networks Algorithm for the Clique Partitioning Problem.
Int. J. Comput. Their Appl., 2002

An evolutionary algorithm for the testable allocation problem in high-level synthesis.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2000
Test insertion at the RT level using functional test metrics.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1993
An improved method for RTL synthesis with testability tradeoffs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Approach for Redesigning in Data Path Synthesis.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
SYNTEST: an environment for system-level design for test.
Proceedings of the conference on European design automation, 1992

1991
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Data Path Synthesis Method for Self-Testable Designs.
Proceedings of the 28th Design Automation Conference, 1991


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