Haidar M. Harmanani

According to our database, Haidar M. Harmanani authored at least 38 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

AraSpot: Arabic Spoken Command Spotting.

Mahmoud Salhab, Haidar Harmanani

CoRR, 2023

2022

Joint theme and event based rating model for identifying relevant influencers on Twitter: COVID-19 case study.

Ali Srour, Hakima Ould-Slimane, Azzam Mourad, Haidar Harmanani, Cathia Jenainatiy

Online Soc. Networks Media, 2022

2021

A Novel Federated Fog Architecture Embedding Intelligent Formation.

Hala Shamseddine, Jana Nizam, Ahmad Hammoud, Azzam Mourad, Hadi Otrok, Haidar Harmanani, Zbigniew Dziong

IEEE Netw., 2021

ABET Accreditation: A Way Forward for PDC Education.

Sherif G. Aly, Haidar Harmanani, Rajendra K. Raj, Sanaa Sharafeddine

Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

A Strength Pareto Evolutionary Algorithm for Solving the Capacitated Vehicle Routing Problem with Time Windows.

Wissam Marrouche, Haidar M. Harmanani

Proceedings of the 13th International Joint Conference on Computational Intelligence, 2021

2020

Critical Impact of Social Networks Infodemic on Defeating Coronavirus COVID-19 Pandemic: Twitter-Based Study and Research Directions.

Azzam Mourad, Ali Srour, Haidar M. Harmanani, Cathia Jenainatiy, Mohamad Arafeh

IEEE Trans. Netw. Serv. Manag., 2020

Cloud federation formation using genetic and evolutionary game theoretical models.

Ahmad Hammoud, Azzam Mourad, Hadi Otrok, Omar Abdel Wahab, Haidar Harmanani

Future Gener. Comput. Syst., 2020

2018

A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules.

Wissam Marrouche, Rana Farah, Haidar M. Harmanani

Int. J. Comput. Intell. Appl., 2018

2016

An enhanced light-load efficiency step down regulator with fine step frequency scaling.

Nijad Anabtawi, Rony Ferzli, Haidar M. Harmanani

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applications.

Nijad Anabtawi, Rony Ferzli, Haidar M. Harmanani

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiers.

Nijad Anabtawi, Rony Ferzli, Haidar M. Harmanani

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A Parallel GPU Implementation of the Timber Wolf Placement Algorithm.

Ahmad Al Kawam, Haidar M. Harmanani

Proceedings of the 12th International Conference on Information Technology, 2015

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components.

Haidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya

Proceedings of the 2015 IEEE International Conference on Information Reuse and Integration, 2015

2014

Efficient shaped quantizer dithering implementation for sigma delta modulators.

Nijad Anabtawi, Rony Ferzli, Haidar M. Harmanani

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012

An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates.

Hassan A. Salamy, Haidar Harmanani

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

Heuristic approaches for optimizing the performance of rule-based classifiers.

Danielle Azar, Haidar M. Harmanani

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2011

An optimal formulation for test scheduling network-on-chip using multiple clock rates.

Hassan A. Salamy, Haidar M. Harmanani

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

A Simulated Annealing Algorithm for the Capacitated Vehicle Routing Problem.

Haidar M. Harmanani, Danielle Azar, Nathalie Helal, Walid Keirouz

Proceedings of the ISCA 26th International Conference on Computers and Their Applications, 2011

2010

Predicting stability of classes in an object-oriented system.

Danielle Azar, Haidar M. Harmanani, Rita Korkmaz

J. Comput. Methods Sci. Eng., 2010

A method for efficient NoC test scheduling using deterministic routing.

Rana Farah, Haidar Harmanani

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Estimating test cost during data path and controller synthesis with low power overhead.

Haidar M. Harmanani, Maya Kodeih

Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2009

A hybrid heuristic approach to optimize rule-based software quality estimation models.

Danielle Azar, Haidar M. Harmanani, Rita Korkmaz

Inf. Softw. Technol., 2009

A parallel genetic algorithm for the open-shop scheduling problem using deterministic and random moves.

Haidar M. Harmanani, Fouad Drouby, Steve Bou Ghosn

Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009

2006

Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm.

Haidar M. Harmanani, Hassan A. Salamy

J. Circuits Syst. Comput., 2006

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints.

Haidar M. Harmanani, Hassan A. Salamy

Int. J. Comput. Intell. Appl., 2006

A Rule-Based Extensible Stemmer for Information Retrieval with Application to Arabic.

Haidar M. Harmanani, Walid Keirouz, Saeed Raheel

Int. Arab J. Inf. Technol., 2006

2005

An Evolutionary Algorithm for the Allocation Problem in High-level Synthesis.

Haidar M. Harmanani, Rony Saliba

J. Circuits Syst. Comput., 2005

A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms.

Haidar Harmanani, Bassem Karablieh

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004

A Parallel Genetic Algorithm For The Geometrically Constrained Site Layout Problem With Unequal-Size Facilities.

Haidar M. Harmanani, Pierrette Zouein, Aouni M. Hajar

Int. J. Comput. Intell. Appl., 2004

2003

A neural networks algorithm for data path synthesis.

Haidar M. Harmanani

Comput. Electr. Eng., 2003

2002

A Parallel Neural Networks Algorithm for the Clique Partitioning Problem.

Haidar M. Harmanani

Int. J. Comput. Their Appl., 2002

An evolutionary algorithm for the testable allocation problem in high-level synthesis.

Haidar Harmanani, Rony Saliba

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2000

Test insertion at the RT level using functional test metrics.

Haidar Harmanani, Salam Harfoush

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1993

An improved method for RTL synthesis with testability tradeoffs.

Haidar Harmanani, Christos A. Papachristou

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Approach for Redesigning in Data Path Synthesis.

Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

SYNTEST: an environment for system-level design for test.

Haidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani

Proceedings of the conference on European design automation, 1992

1991

SYNTEST: A Method for High-Level SYNthesis with Self-TESTability.

Christos A. Papachristou, Scott Chiu, Haidar Harmanani

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Data Path Synthesis Method for Self-Testable Designs.

Christos A. Papachristou, Scott Chiu, Haidar Harmanani

Proceedings of the 28th Design Automation Conference, 1991