Haiqiu Huang

Orcid: 0009-0008-6366-7386

According to our database¹, Haiqiu Huang authored at least 3 papers between 2024 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2025

A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

2024

Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations.

[BibT_eX]

[DOI]

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Haiqiu Huang

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