Baiqing Zhong
Orcid: 0009-0001-7455-815X
According to our database1,
Baiqing Zhong authored at least 7 papers
between 2023 and 2026.
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Bibliography
2026
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026
2025
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025
C3ache: Towards Hierarchical Cache-Centric Computing for Sparse Matrix Multiplication on GPGPUs.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025
2024
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
2023
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023