Hao Deng

Orcid: 0000-0002-7193-7939

Affiliations:
  • University of Houston, Department of Electrical and Computer Engineering, TX, USA


According to our database1, Hao Deng authored at least 13 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 23.4-27.6 GHz "Zig-Zag" VCO with Continuous Frequency Switching for FMCW Radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 71-86 GHz Cascaded Harmonic Enhanced Tripler with -69 dBc Fundamental and -66 dBc Second Harmonic Suppression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers.
Sensors, 2021

A 64-84 GHz CMOS LNA with Excellent Gain Flatness for Wideband mmW Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019


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