Phaneendra Bikkina

According to our database, Phaneendra Bikkina authored at least 6 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.

Hao Deng, Phaneendra Bikkina, Esko Mikkola, Runxi Zhang, Jinghong Chen

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation.

Yulang Feng, Hao Deng, Qingjun Fan, Yuxuan Tang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen

IEEE Trans. Very Large Scale Integr. Syst., 2022

2020

An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology.

Yulang Feng, Qingjun Fan, Hao Deng, Jeffrey Chen, Runxi Zhang, Phaneendra Bikkina, Jinghong Chen

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.

Yulang Feng, Hao Deng, Qingjun Fan, Runxi Zhang, Phaneendra Bikkina, Jinghong Chen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator.

Qingjun Fan, Runxi Zhang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017

RFI mitigating receiver back-end for radiometers.

Phaneendra Bikkina, Qingjun Fan, Wenlan Wu, Jinghong Chen, Esko Mikkola

Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017