Qingjun Fan
Orcid: 0000-0002-6464-6498Affiliations:
- University of Houston, Texas, USA
According to our database1,
Qingjun Fan
authored at least 17 papers
between 2016 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2020
IEEE J. Solid State Circuits, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017
2016
Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016