Harshit Naman
According to our database1,
Harshit Naman authored at least 4 papers
between 2025 and 2026.
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Bibliography
2026
25.3 A 16nm 0.042mm<sup>2</sup> 0.66μJ/Ops Lightweight MLWE PQC KEM with Cryptanalysis-ASIC Co-Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel Receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A Real-Time Memory-Less In-Sensor Time-Domain Convolution Processor with Programmable Kernel for Feature Extraction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
TD-dAJC: A 2pJ/Pixel Time-Domain Weight and Integrating-MAC Based Direct-Analog-to-MJPEG Compression for Video Sensor Nodes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025